Derived tx_rst_arr from tr_rst for u_txc_rx_channelaligned_arr.

libraries/technology/xaui/tech_xaui_stratixiv.vhd

@@ -98,6 +98,7 @@ ARCHITECTURE str OF tech_xaui_stratixiv IS
   SIGNAL a_rx_ready_arr            : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);  -- rx_ready in mm_clk clock domain
   
   SIGNAL a_rx_channelaligned_arr   : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);  -- rx_channelaligned asynchronous, indicates that all 4 RX channels are aligned when asserted
+  SIGNAL tx_rst_arr                : STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);
   
   SIGNAL xaui_mosi_arr             : t_mem_mosi_arr(g_nof_xaui-1 DOWNTO 0);
   SIGNAL xaui_miso_arr             : t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0); 
@@ -125,13 +126,24 @@ BEGIN
       din  => a_rx_ready_arr(i),
       dout => rxc_rx_ready_arr(i)
     );
+    
+    u_areset_tx_rst : ENTITY common_lib.common_areset
+    GENERIC MAP(
+      g_rst_level => '1',
+      g_delay_len => 4
+    )
+    PORT MAP(
+      clk     => tx_clk_arr(i),
+      in_rst  => tr_rst,
+      out_rst => tx_rst_arr(i)
+    );    
 
     u_txc_rx_channelaligned_arr: ENTITY work.tech_xaui_align_dly
-    GENERIC MAP(
-      g_align_dly_cnt => sel_a_b(g_sim, 50, 156250000);  -- about 1 second on hw    
+    GENERIC MAP (
+      g_sim => g_sim    -- to use shorter delay when in simulation
     )
     PORT MAP(
-      tx_rst                    => i_tx_rst_arr(i),
+      tx_rst                    => tx_rst_arr(i),
       tx_clk                    => tx_clk_arr(i),
 
       a_rx_channelaligned       => a_rx_channelaligned_arr(i),