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RTSD
HDL
Commits
4aa3cb95
Commit
4aa3cb95
authored
10 years ago
by
Eric Kooistra
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back to using g_sim instead of g_align_dly_cnt.
parent
110c4345
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libraries/technology/xaui/tech_xaui_align_dly.vhd
+5
-4
5 additions, 4 deletions
libraries/technology/xaui/tech_xaui_align_dly.vhd
with
5 additions
and
4 deletions
libraries/technology/xaui/tech_xaui_align_dly.vhd
+
5
−
4
View file @
4aa3cb95
...
...
@@ -22,7 +22,7 @@
-- Purpose: Define that other side must be aligned within some delay after this side got aligned.
-- Description:
-- We assume the RX connected to our TX will be channel aligned within
g
_align_dly_cnt cycles
-- We assume the RX connected to our TX will be channel aligned within
c
_align_dly_cnt cycles
-- after 'our own' RX has asserted channelaligned. This is important because txc_tx_channelaligned_dly
-- connects directly to tx_siso.ready.
-- Assert txc_rx_channelaligned: basically indicates whether or not the RX of the receiving
...
...
@@ -35,7 +35,7 @@ USE common_lib.common_mem_pkg.ALL;
ENTITY
tech_xaui_align_dly
IS
GENERIC
(
g_
align_dly_cnt
:
NATURAL
:
=
156250000
);
-- about 1 second on hw
g_
sim
:
BOOLEAN
:
=
FALSE
);
PORT
(
tx_clk
:
IN
STD_LOGIC
;
...
...
@@ -50,7 +50,8 @@ END tech_xaui_align_dly;
ARCHITECTURE
rtl
OF
tech_xaui_align_dly
IS
-- FSM to delay txc_rx_channelaligned (txc_rx_channelaligned_dly is connected to tx_siso.ready)
CONSTANT
c_align_dly_cnt_w
:
NATURAL
:
=
ceil_log2
(
g_align_dly_cnt
);
CONSTANT
c_align_dly_cnt
:
NATURAL
:
=
sel_a_b
(
g_sim
,
50
,
156250000
);
-- about 1 second on hw
CONSTANT
c_align_dly_cnt_w
:
NATURAL
:
=
ceil_log2
(
c_align_dly_cnt
);
TYPE
t_state_enum
IS
(
s_init
,
s_aligned
,
s_aligned_dly
);
...
...
@@ -107,7 +108,7 @@ BEGIN
WHEN
s_aligned
=>
-- We assume the connecting RX is aligned after this delay...
nxt_txc_align_dly_cycle_cnt
<=
INCR_UVEC
(
txc_align_dly_cycle_cnt
,
1
);
IF
txc_align_dly_cycle_cnt
=
TO_UVEC
(
g
_align_dly_cnt
,
c_align_dly_cnt_w
)
THEN
IF
txc_align_dly_cycle_cnt
=
TO_UVEC
(
c
_align_dly_cnt
,
c_align_dly_cnt_w
)
THEN
nxt_txc_rx_channelaligned_dly
<=
'1'
;
nxt_state
<=
s_aligned_dly
;
END
IF
;
...
...
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