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Commit aaf62b8f authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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changed the ATXPLL selecting from 1-24 to 1-12. Either 1 ATXPLL will 

drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)
parent 08d9a16e
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libraries/technology/10gbase_r/hdllib.cfg
+ 2
− 2
View file @ aaf62b8f
......@@ -3,10 +3,10 @@ hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology
tech_pll
ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_24
ip_arria10_phy_10gbase_r_12
ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_12
tech_transceiver
common
hdl_lib_uses_sim =
......
libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+ 44
− 44
View file @ aaf62b8f
......@@ -22,10 +22,10 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150;
LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150;
LIBRARY ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150;
LIBRARY ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150;
LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
......@@ -62,7 +62,7 @@ END tech_10gbase_r_arria10;
ARCHITECTURE str OF tech_10gbase_r_arria10 IS
CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 24
CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=12, 12, 1); -- only support single 1 or block of 12
CONSTANT IP_SIZE : NATURAL := c_nof_channels_per_ip; -- short constant name alias to improve index readability
CONSTANT IP_SIZE_DATA : NATURAL := IP_SIZE * c_xgmii_data_w;
......@@ -194,7 +194,7 @@ BEGIN
END GENERATE;
END GENERATE;
gen_phy_24 : IF c_nof_channels_per_ip=24 GENERATE
gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
......@@ -206,49 +206,49 @@ BEGIN
rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
END GENERATE;
u_ip_arria10_phy_10gbase_r_24 : ip_arria10_phy_10gbase_r_24
u_ip_arria10_phy_10gbase_r_12 : ip_arria10_phy_10gbase_r_12
PORT MAP (
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
--rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
--tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
--tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
--tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_pma_div_clkout : out std_logic_vector(23 downto 0); -- tx_pma_div_clkout.clk
--rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
--rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
--tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
--tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
--rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
--rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
--unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
--unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
......@@ -256,22 +256,22 @@ BEGIN
--unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
u_ip_arria10_transceiver_reset_controller_24 : ip_arria10_transceiver_reset_controller_24
u_ip_arria10_transceiver_reset_controller_12 : ip_arria10_transceiver_reset_controller_12
PORT MAP (
clock => clk_156, -- : in std_logic := '0'; -- clock.clk
pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset => rst_156, -- : in std_logic := '0'; -- reset.reset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END GENERATE;
......
libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+ 49
− 49
View file @ aaf62b8f
......@@ -73,46 +73,46 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
COMPONENT ip_arria10_phy_10gbase_r_24 IS
COMPONENT ip_arria10_phy_10gbase_r_12
PORT (
rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
tx_pma_div_clkout : out std_logic_vector(23 downto 0); -- tx_pma_div_clkout.clk
tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
END COMPONENT;
......@@ -147,22 +147,22 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
COMPONENT ip_arria10_transceiver_reset_controller_24 IS
COMPONENT ip_arria10_transceiver_reset_controller_12
PORT (
clock : in std_logic := '0'; -- clock.clk
pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset : in std_logic := '0'; -- reset.reset
rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END COMPONENT;
......
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