-Fixed MM bus address widths.

libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd

@@ -102,9 +102,6 @@ ENTITY mmm_unb1_dp_offload IS
     eth1g_ram_mosi                 : OUT t_mem_mosi;  
     eth1g_ram_miso                 : IN  t_mem_miso;
 
-    reg_dp_offload_tx_mosi         : OUT t_mem_mosi; 
-    reg_dp_offload_tx_miso         : IN  t_mem_miso;
-
     reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi; 
     reg_dp_offload_tx_hdr_dat_miso : IN  t_mem_miso;
 
@@ -235,9 +232,6 @@ BEGIN
     u_mm_file_ram_diag_bg               : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
                                                      PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
 
-    u_mm_file_reg_dp_offload_tx         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
-                                                     PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
-
     u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
                                                      PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
 
@@ -388,15 +382,6 @@ BEGIN
       coe_write_export_from_the_ram_diag_bg                   => ram_diag_bg_mosi.wr,
       coe_writedata_export_from_the_ram_diag_bg               => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
-      -- the_reg_dp_offload_tx
-      coe_address_export_from_the_reg_dp_offload_tx           => reg_dp_offload_tx_mosi.address(c_reg_dp_offload_tx_multi_adr_w-1 DOWNTO 0),
-      coe_clk_export_from_the_reg_dp_offload_tx               => OPEN,
-      coe_read_export_from_the_reg_dp_offload_tx              => reg_dp_offload_tx_mosi.rd,
-      coe_readdata_export_to_the_reg_dp_offload_tx            => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
-      coe_reset_export_from_the_reg_dp_offload_tx             => OPEN,
-      coe_write_export_from_the_reg_dp_offload_tx             => reg_dp_offload_tx_mosi.wr,
-      coe_writedata_export_from_the_reg_dp_offload_tx         => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
       -- the_reg_dp_offload_tx_hdr_dat
       coe_address_export_from_the_reg_dp_offload_tx_hdr_dat   => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w-1 DOWNTO 0),
       coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat       => OPEN,

libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd

@@ -171,8 +171,6 @@ ARCHITECTURE str OF unb1_dp_offload IS
   SIGNAL ram_diag_bg_mosi               : t_mem_mosi;
   SIGNAL ram_diag_bg_miso               : t_mem_miso;
 
-  SIGNAL reg_dp_offload_tx_mosi         : t_mem_mosi;
-  SIGNAL reg_dp_offload_tx_miso         : t_mem_miso;
   SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
   SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
   SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
@@ -532,9 +530,6 @@ BEGIN
     reg_diag_bg_mosi               => reg_diag_bg_mosi,
     reg_diag_bg_miso               => reg_diag_bg_miso,
 
-    reg_dp_offload_tx_mosi         => reg_dp_offload_tx_mosi,
-    reg_dp_offload_tx_miso         => reg_dp_offload_tx_miso,
-
     reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
     reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,