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applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator_nodes.vhd 0 → 100644
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, correlator_lib, filter_lib, fft_lib, rTwoSDF_lib, diag_lib, dp_lib, eth_lib, tech_tse_lib, tr_10GbE_lib, apertif_lib, wpfb_lib, bf_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE filter_lib.fil_pkg.ALL;
USE fft_lib.fft_pkg.ALL;
USE rTwoSDF_lib.rTwoSDFPkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE apertif_lib.apertif_udp_offload_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
USE work.apertif_unb1_correlator_pkg.ALL;
-- Purpose:
-- . Calculate all cross- and autocorrelations of the incoming beamlets
-- Description:
-- . The incpoming beamlets (3x 10GbE from fn_beamformer) are distributed among the 8 FPGAs per board; each FPGA correlates
-- 1/8th of the beamlets.
-- Remarks:
-- . The BG version (g_use_bg=TRUE) functionally works.
-- . The 10G-input version (no BG) needs the DDR3 transpose in fn_beamformer to be in place.
-- . fn_beamformer now outputs 176/256 beamlets but this might be increased to 192/256 (9.6Gbps) again as its 10G issue is solved.
-- . URGENT:
-- . We need 9b filter coefficients before we can synthesize including the mesh terminals! --FIXME
-- . Note: the 18b coeffieciens *do* fit and meet timing with only BG (without 10G RX stage).
-- . Other:
-- . Synthesis incl. mesh terminals went OK but used 96% of the logic resources.
-- . Keep an eye on the FIXME marks.
ENTITY apertif_unb1_correlator_nodes IS
GENERIC (
g_design_name : STRING := "apertif_unb1_correlator";
g_design_note : STRING := "revision info";
g_use_bg : BOOLEAN := FALSE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
g_sim : BOOLEAN := FALSE; -- Overridden by TB
g_sim_level : NATURAL := 0;
g_sim_fast : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_use_dumb_mesh_terminals : BOOLEAN := FALSE -- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
sens_sd : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_clk : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- SerDes Clock BN-BI / SI_FN
SB_CLK : IN STD_LOGIC := '0'; -- SerDes clock FN-BN (tr_mesh)
-- Mesh Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-- Serial I/O: 10GbE receivers
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-- So we need to assign a '1' to it.
);
END apertif_unb1_correlator_nodes;
ARCHITECTURE str OF apertif_unb1_correlator_nodes IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 5);
-- Enable block generators
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, sel_a_b(g_use_bg, 0, 1), 0, 0, 0, 0, 0, 1);
CONSTANT c_nof_nodes : NATURAL := 8;
CONSTANT c_nof_10GbE_streams : NATURAL := 3; -- The number of 10G input streams
CONSTANT c_nof_bf_modules : NATURAL := c_bf.nof_bf_units; -- We have 4 BF modules here because each sending fn_beamformer design has 4 bf units.
CONSTANT c_compl_dat_w : NATURAL := 8;
CONSTANT c_use_input_node : BOOLEAN := func_rev_selector(g_design_name, "c_use_input_node");
CONSTANT c_use_mesh_node : BOOLEAN := func_rev_selector(g_design_name, "c_use_mesh_node");
CONSTANT c_use_processing_node : BOOLEAN := func_rev_selector(g_design_name, "c_use_processing_node");
CONSTANT c_use_bg_input : BOOLEAN := func_rev_selector(g_design_name, "c_use_bg_input");
CONSTANT c_use_db_input : BOOLEAN := func_rev_selector(g_design_name, "c_use_db_input");
CONSTANT c_use_bg_mesh : BOOLEAN := func_rev_selector(g_design_name, "c_use_bg_mesh");
CONSTANT c_use_db_mesh : BOOLEAN := func_rev_selector(g_design_name, "c_use_db_mesh");
CONSTANT c_use_interleave : BOOLEAN := func_rev_selector(g_design_name, "c_use_interleave");
CONSTANT c_use_wpfb : BOOLEAN := func_rev_selector(g_design_name, "c_use_wpfb");
CONSTANT c_use_repack : BOOLEAN := func_rev_selector(g_design_name, "c_use_repack");
CONSTANT c_mesh_data_w : NATURAL := sel_a_b(g_design_name = "apertif_unb1_correlator_mesh_ref", 16, 48);
CONSTANT c_usr_data_w : NATURAL := 16;
CONSTANT c_bg_file_name_prefix : STRING := "hex/composite_signals";
-- BSN Alignern + FIFO's
CONSTANT c_block_period : NATURAL := 186; --256; --FIXME: first block size was 176/256. Now 128/186,18 (non-integer...), assuming 186 is OK.
CONSTANT c_block_size : NATURAL := 128; --176
CONSTANT c_bsn_align_latency : NATURAL := 3;
CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
CONSTANT c_nof_blocks_per_sync : NATURAL := 800000;
CONSTANT c_bsn_sync_time_out : NATURAL := (c_block_period * c_nof_blocks_per_sync * 10)/8; --*10/8 as margin
-- Re- and Deinterleaver
CONSTANT c_use_complex : BOOLEAN := TRUE;
-- Correlator
CONSTANT c_nof_visibility_streams : NATURAL := 1;
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL epcs_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL sa_rst : STD_LOGIC;
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
-- MM Register interfaces
SIGNAL reg_wdi_mosi : t_mem_mosi;
SIGNAL reg_wdi_miso : t_mem_miso;
SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
SIGNAL reg_unb_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
SIGNAL eth1g_ram_mosi : t_mem_mosi;
SIGNAL eth1g_ram_miso : t_mem_miso;
SIGNAL eth1g_reg_mosi : t_mem_mosi;
SIGNAL eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_tse_mosi : t_mem_mosi;
SIGNAL eth1g_tse_miso : t_mem_miso;
SIGNAL reg_diag_bg_input_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_input_miso : t_mem_miso;
SIGNAL reg_diag_bg_mesh_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_mesh_miso : t_mem_miso;
SIGNAL ram_diag_bg_mesh_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_mesh_miso : t_mem_miso;
SIGNAL reg_diagnostics_mosi : t_mem_mosi;
SIGNAL reg_diagnostics_miso : t_mem_miso;
SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_input_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_input_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_input_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_input_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mesh_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_mesh_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mesh_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_mesh_miso : t_mem_miso;
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
SIGNAL reg_mdio_0_mosi : t_mem_mosi;
SIGNAL reg_mdio_0_miso : t_mem_miso;
SIGNAL reg_mdio_1_mosi : t_mem_mosi;
SIGNAL reg_mdio_1_miso : t_mem_miso;
SIGNAL reg_mdio_2_mosi : t_mem_mosi;
SIGNAL reg_mdio_2_miso : t_mem_miso;
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
SIGNAL reg_tr_10gbe_miso : t_mem_miso;
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_miso : t_mem_miso;
SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- BSN monitors
SIGNAL dp_bsn_monitor_in_siso_arr : t_dp_siso_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
SIGNAL dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_visibility_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_visibility_streams-1 DOWNTO 0);
SIGNAL mesh_data_in_sosi_arr : t_dp_sosi_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL mesh_data_in_siso_arr : t_dp_siso_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL mesh_data_out_sosi_arr : t_dp_sosi_arr(c_nof_nodes-1 DOWNTO 0);
SIGNAL mesh_data_out_siso_arr : t_dp_siso_arr(c_nof_nodes-1 DOWNTO 0);
BEGIN
gen_node_input : IF c_use_input_node = TRUE GENERATE
u_input_node : ENTITY work.node_apertif_unb1_correlator_input
GENERIC MAP (
g_sim => g_sim, --: BOOLEAN := FALSE; -- Overridden by TB
g_use_bg => c_use_bg_input, --: BOOLEAN := FALSE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
g_use_db => c_use_db_input, --: BOOLEAN := FALSE; -- Enable the databuffers when set tot TRUE.
g_use_interleave => c_use_interleave,
g_bg_file_name_prefix => c_bg_file_name_prefix, --: STRING := "hex/composite_signals";
g_usr_data_w => c_usr_data_w, --: NATURAL := 16; -- Specifies the datawidth of Re + Im
g_nof_output_streams => c_nof_nodes --: NATURAL := 8 -- 8 Indicates the number of output streams, where each stream is targetting a unique node.
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- Output array
data_src_out_arr => mesh_data_in_sosi_arr,
data_src_in_arr => mesh_data_in_siso_arr,
-- MM
reg_diag_bg_mosi => reg_diag_bg_input_mosi,
reg_diag_bg_miso => reg_diag_bg_input_miso,
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso,
reg_mdio_mosi_arr => reg_mdio_mosi_arr,
reg_mdio_miso_arr => reg_mdio_miso_arr,
ram_diag_data_buf_mosi => ram_diag_data_buf_input_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_input_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_input_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_input_miso,
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-- Transceiver clocks
SA_CLK => SA_CLK,
-- Serial I/O: 10GbE receivers
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_3_TX => SI_FN_3_TX,
SI_FN_3_RX => SI_FN_3_RX,
SI_FN_0_CNTRL => SI_FN_0_CNTRL,
SI_FN_1_CNTRL => SI_FN_1_CNTRL,
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN
);
END GENERATE;
gen_node_mesh : IF c_use_mesh_node = TRUE GENERATE
u_mesh_node : ENTITY work.node_apertif_unb1_correlator_mesh
GENERIC MAP(
g_sim => g_sim,
g_sim_level => g_sim_level,
g_sim_node_nr => g_sim_node_nr,
g_node_type => e_any,
g_use_bg => c_use_bg_mesh,
g_use_db => c_use_db_mesh,
g_nof_input_streams => c_nof_nodes,
g_nof_output_streams => c_nof_nodes,
g_use_repack => c_use_repack,
g_usr_use_complex => c_use_complex,
g_usr_data_w => c_mesh_data_w,
g_usr_frame_len => 128,
g_aux => c_unb1_board_aux
)
PORT MAP(
-- System
chip_id => this_chip_id,
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
tr_mesh_clk => SB_clk,
cal_clk => cal_clk,
-- Input array
data_snk_in_arr => mesh_data_in_sosi_arr,
data_snk_out_arr => mesh_data_in_siso_arr,
-- Output array
data_src_out_arr => mesh_data_out_sosi_arr,
data_src_in_arr => mesh_data_out_siso_arr,
-- MM interface
reg_diag_bg_mosi => reg_diag_bg_mesh_mosi,
reg_diag_bg_miso => reg_diag_bg_mesh_miso,
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso,
ram_diag_data_buf_mosi => ram_diag_data_buf_mesh_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_mesh_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mesh_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_mesh_miso,
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX
);
END GENERATE;
gen_no_node_mesh : IF c_use_mesh_node = FALSE GENERATE
mesh_data_out_sosi_arr <= mesh_data_in_sosi_arr;
mesh_data_in_siso_arr <= mesh_data_out_siso_arr;
END GENERATE;
gen_node_processing : IF c_use_processing_node = TRUE GENERATE
u_node_processing : ENTITY work.apertif_unb1_correlator_processing
GENERIC MAP (
g_sim => g_sim,
g_sim_fast => g_sim_fast,
g_use_wpfb => c_use_wpfb,
g_usr_data_w => c_usr_data_w,
g_nof_input_streams => c_nof_nodes,
g_nof_output_streams => c_nof_visibility_streams
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ID => ID,
-- Input array
data_snk_in_arr => mesh_data_out_sosi_arr,
data_snk_out_arr => mesh_data_out_siso_arr,
-- Output array
data_src_out_arr => dp_offload_tx_src_out_arr,
data_src_in_arr => dp_offload_tx_src_in_arr,
-- MM
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso
);
END GENERATE;
-----------------------------------------------------------------------------
-- RX: BSN monitors at several stages in the stream
-----------------------------------------------------------------------------
-- u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
-- GENERIC MAP (
-- g_nof_streams => 5,
-- g_sync_timeout => c_bsn_sync_time_out,
-- g_log_first_bsn => TRUE
-- )
-- PORT MAP (
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
-- reg_mosi => reg_bsn_monitor_mosi,
-- reg_miso => reg_bsn_monitor_miso,
--
-- dp_rst => dp_rst,
-- dp_clk => dp_clk,
-- in_siso_arr => dp_bsn_monitor_in_siso_arr,
-- in_sosi_arr => dp_bsn_monitor_in_sosi_arr
-- );
--
-- -- 0) Monitor the BSN-aligned output
-- dp_bsn_monitor_in_sosi_arr(0) <= dp_bsn_align_src_out_arr(0);
-- dp_bsn_monitor_in_siso_arr(0) <= dp_bsn_align_src_in_arr(0);
-- -- 1) Monitor the rewired/reinterleaver stage output / WPFB input
-- dp_bsn_monitor_in_sosi_arr(1) <= wpfb_snk_in_arr(0);
-- dp_bsn_monitor_in_siso_arr(1) <= c_dp_siso_rdy;
-- -- 2) Monitor the WPFB output / correlator input
-- dp_bsn_monitor_in_sosi_arr(2) <= wpfb_src_out_arr(0);
-- dp_bsn_monitor_in_siso_arr(2) <= c_dp_siso_rdy;
-- -- 3) Monitor the correlator output / visibility offload input
-- dp_bsn_monitor_in_sosi_arr(3) <= correlator_src_out_arr(0);
-- dp_bsn_monitor_in_siso_arr(3) <= c_dp_siso_rdy;
-- -- 3) Monitor the correlator output / visibility offload input
-- dp_bsn_monitor_in_sosi_arr(4) <= dp_offload_tx_src_out_arr(0);
-- dp_bsn_monitor_in_siso_arr(4) <= dp_offload_tx_src_in_arr(0);
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
g_sim => g_sim,
g_sim_flash_model => FALSE,
g_design_name => g_design_name,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_udp_offload => TRUE,
g_udp_offload_nof_streams => 1,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux,
g_dp_clk_use_pll => TRUE,
g_xo_clk_use_pll => TRUE
)
PORT MAP (
-- Clock and reset signals
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk_out => mm_clk,
mm_clk => mm_clk,
mm_rst => mm_rst,
mm_locked => mm_locked,
mm_locked_out => mm_locked,
epcs_clk => epcs_clk,
epcs_clk_out => epcs_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
cal_rec_clk => cal_clk,
this_chip_id => this_chip_id,
-- Toggle WDI
pout_wdi => pout_wdi,
-- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_clk_out => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports
udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
udp_tx_siso_arr => dp_offload_tx_src_in_arr,
-- FPGA pins
-- . General
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- . Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
-- . 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_apertif_unb1_correlator : ENTITY work.mmm_apertif_unb1_correlator
GENERIC MAP(
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr
)
PORT MAP(
mm_clk => mm_clk,
mm_rst => mm_rst,
pout_wdi => pout_wdi,
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
reg_diag_bg_input_mosi => reg_diag_bg_input_mosi,
reg_diag_bg_input_miso => reg_diag_bg_input_miso,
reg_diag_bg_mesh_mosi => reg_diag_bg_mesh_mosi,
reg_diag_bg_mesh_miso => reg_diag_bg_mesh_miso,
ram_diag_bg_mesh_mosi => ram_diag_bg_mesh_mosi,
ram_diag_bg_mesh_miso => ram_diag_bg_mesh_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
reg_diag_data_buf_input_mosi => reg_diag_data_buf_input_mosi,
reg_diag_data_buf_input_miso => reg_diag_data_buf_input_miso,
ram_diag_data_buf_input_mosi => ram_diag_data_buf_input_mosi,
ram_diag_data_buf_input_miso => ram_diag_data_buf_input_miso,
reg_diag_data_buf_mesh_mosi => reg_diag_data_buf_mesh_mosi,
reg_diag_data_buf_mesh_miso => reg_diag_data_buf_mesh_miso,
ram_diag_data_buf_mesh_mosi => ram_diag_data_buf_mesh_mosi,
ram_diag_data_buf_mesh_miso => ram_diag_data_buf_mesh_miso,
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
reg_mdio_0_mosi => reg_mdio_0_mosi,
reg_mdio_0_miso => reg_mdio_0_miso,
reg_mdio_1_mosi => reg_mdio_1_mosi,
reg_mdio_1_miso => reg_mdio_1_miso,
reg_mdio_2_mosi => reg_mdio_2_mosi,
reg_mdio_2_miso => reg_mdio_2_miso,
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
reg_tr_10gbe_miso => reg_tr_10gbe_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso,
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso
);
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
reg_mdio_mosi_arr(2) <= reg_mdio_2_mosi;
reg_mdio_0_miso <= reg_mdio_miso_arr(0);
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
-- u_mmm : ENTITY work.mmm_apertif_unb1_correlator
-- GENERIC MAP (
-- g_sim => g_sim,
-- g_sim_unb_nr => g_sim_unb_nr,
-- g_sim_node_nr => g_sim_node_nr,
-- g_wpfb => c_wpfb,
-- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr
-- )
-- PORT MAP(
-- xo_clk => xo_clk,
-- xo_rst_n => xo_rst_n,
-- xo_rst => xo_rst,
--
-- mm_rst => mm_rst,
-- mm_clk => mm_clk,
-- mm_locked => mm_locked,
--
-- -- PIOs
-- pout_wdi => pout_wdi,
--
-- -- Manual WDI override
-- reg_wdi_mosi => reg_wdi_mosi,
-- reg_wdi_miso => reg_wdi_miso,
--
-- -- system_info
-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
-- reg_unb_system_info_miso => reg_unb_system_info_miso,
-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
-- rom_unb_system_info_miso => rom_unb_system_info_miso,
--
-- -- UniBoard I2C sensors
-- reg_unb_sens_mosi => reg_unb_sens_mosi,
-- reg_unb_sens_miso => reg_unb_sens_miso,
--
-- -- PPSH
-- reg_ppsh_mosi => reg_ppsh_mosi,
-- reg_ppsh_miso => reg_ppsh_miso,
--
-- -- Block generator input
-- reg_diag_bg_input_mosi => reg_diag_bg_input_mosi,
-- reg_diag_bg_input_miso => reg_diag_bg_input_miso,
--
-- -- Block generator mesh
-- reg_diag_bg_mesh_mosi => reg_diag_bg_mesh_mosi,
-- reg_diag_bg_mesh_miso => reg_diag_bg_mesh_miso,
-- ram_diag_bg_mesh_mosi => ram_diag_bg_mesh_mosi,
-- ram_diag_bg_mesh_miso => ram_diag_bg_mesh_miso,
--
-- -- 10 GbE
-- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
-- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
-- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
-- reg_tr_xaui_miso => reg_tr_xaui_miso,
-- reg_mdio_mosi_arr => reg_mdio_mosi_arr,
-- reg_mdio_miso_arr => reg_mdio_miso_arr,
--
-- -- DP offload RX
-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
--
-- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
-- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
--
-- -- . Data buffers input
-- reg_diag_data_buf_input_mosi => reg_diag_data_buf_input_mosi,
-- reg_diag_data_buf_input_miso => reg_diag_data_buf_input_miso,
-- ram_diag_data_buf_input_mosi => ram_diag_data_buf_input_mosi,
-- ram_diag_data_buf_input_miso => ram_diag_data_buf_input_miso,
--
-- -- . Data buffers mesh
-- reg_diag_data_buf_mesh_mosi => reg_diag_data_buf_mesh_mosi,
-- reg_diag_data_buf_mesh_miso => reg_diag_data_buf_mesh_miso,
-- ram_diag_data_buf_mesh_mosi => ram_diag_data_buf_mesh_mosi,
-- ram_diag_data_buf_mesh_miso => ram_diag_data_buf_mesh_miso,
--
-- -- 1GbE visibility offload TX
-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
--
-- -- Filter coefficients
-- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
-- ram_fil_coefs_miso => ram_fil_coefs_miso,
--
-- -- eth1g
-- eth1g_tse_clk => eth1g_tse_clk,
-- eth1g_mm_rst => eth1g_mm_rst,
-- eth1g_tse_mosi => eth1g_tse_mosi,
-- eth1g_tse_miso => eth1g_tse_miso,
-- eth1g_reg_mosi => eth1g_reg_mosi,
-- eth1g_reg_miso => eth1g_reg_miso,
-- eth1g_reg_interrupt => eth1g_reg_interrupt,
-- eth1g_ram_mosi => eth1g_ram_mosi,
-- eth1g_ram_miso => eth1g_ram_miso
-- );
END str;
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator_pkg.vhd 0 → 100644
+ 90
− 0
View file @ aa679d79
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
PACKAGE apertif_unb1_correlator_pkg IS
CONSTANT c_nof_revisions : NATURAL := 4;
CONSTANT c_nof_constants : NATURAL := 10;
TYPE t_apertif_unb1_correlator_revision_matrix IS ARRAY(INTEGER RANGE 0 TO c_nof_constants-1, INTEGER RANGE 0 TO c_nof_revisions-1) OF BOOLEAN;
CONSTANT c_apertif_unb1_correlator_revision_matrix : t_apertif_unb1_correlator_revision_matrix :=
(-- 0 1 2 3
( TRUE, TRUE, TRUE, FALSE), -- c_use_input_node
( TRUE, TRUE, TRUE, TRUE), -- c_use_mesh_node
( TRUE, TRUE, TRUE, FALSE), -- c_use_processing_node
( TRUE, TRUE, TRUE, FALSE), -- c_use_bg_input
( TRUE, TRUE, TRUE, FALSE), -- c_use_db_input
( TRUE, TRUE, TRUE, FALSE), -- c_use_interleave
( TRUE, TRUE, TRUE, TRUE), -- c_use_bg_mesh
( TRUE, TRUE, TRUE, TRUE), -- c_use_db_mesh
( TRUE, TRUE, TRUE, FALSE), -- c_use_repack
( TRUE, TRUE, TRUE, FALSE) -- c_use_wpfb
);
FUNCTION func_revision_number(g_design_name : STRING) RETURN NATURAL;
FUNCTION func_constant_number(c_name : STRING) RETURN NATURAL;
FUNCTION func_rev_selector(g_design_name, c_name : STRING) RETURN BOOLEAN;
END apertif_unb1_correlator_pkg;
PACKAGE BODY apertif_unb1_correlator_pkg IS
FUNCTION func_revision_number(g_design_name : STRING) RETURN NATURAL IS
BEGIN
IF g_design_name = "apertif_unb1_correlator_full" THEN RETURN 0;
ELSIF g_design_name = "apertif_unb1_correlator_lite" THEN RETURN 1;
ELSIF g_design_name = "apertif_unb1_correlator_lite_bg" THEN RETURN 2;
ELSIF g_design_name = "apertif_unb1_correlator_mesh_ref" THEN RETURN 3;
ELSE RETURN 0;
END IF;
END;
FUNCTION func_constant_number(c_name : STRING) RETURN NATURAL IS
BEGIN
IF c_name = "c_use_input_node" THEN RETURN 0;
ELSIF c_name = "c_use_mesh_node" THEN RETURN 1;
ELSIF c_name = "c_use_processing_node" THEN RETURN 2;
ELSIF c_name = "c_use_bg_input" THEN RETURN 3;
ELSIF c_name = "c_use_db_input" THEN RETURN 4;
ELSIF c_name = "c_use_interleave" THEN RETURN 5;
ELSIF c_name = "c_use_bg_mesh" THEN RETURN 6;
ELSIF c_name = "c_use_db_mesh" THEN RETURN 7;
ELSIF c_name = "c_use_repack" THEN RETURN 8;
ELSIF c_name = "c_use_wpfb" THEN RETURN 9;
ELSE RETURN 0;
END IF;
END;
FUNCTION func_rev_selector(g_design_name, c_name : STRING) RETURN BOOLEAN IS
VARIABLE v_rev_index : NATURAL := func_revision_number(g_design_name);
VARIABLE v_con_index : NATURAL := func_constant_number(c_name);
BEGIN
RETURN c_apertif_unb1_correlator_revision_matrix(v_con_index, v_rev_index);
END;
END apertif_unb1_correlator_pkg;
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