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Commit e27b44ae authored by Pepping's avatar Pepping
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New mmm, generated with script

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applications/apertif/designs/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
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-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
......@@ -17,399 +17,506 @@
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, wpfb_lib, eth_lib, tech_tse_lib, technology_lib;
--------------------------------------------------------------------------------
-- u_inst_mmm_apertif_unb1_correlator : ENTITY work.mmm_apertif_unb1_correlator
-- GENERIC MAP(
-- g_sim => g_sim,
-- g_sim_unb_nr => g_sim_unb_nr,
-- g_sim_node_nr => g_sim_node_nr
-- )
-- PORT MAP(
-- mm_clk => mm_clk,
-- mm_rst => mm_rst,
-- pout_wdi => pout_wdi,
-- reg_wdi_mosi => reg_wdi_mosi,
-- reg_wdi_miso => reg_wdi_miso,
-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
-- reg_unb_system_info_miso => reg_unb_system_info_miso,
-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
-- rom_unb_system_info_miso => rom_unb_system_info_miso,
-- reg_unb_sens_mosi => reg_unb_sens_mosi,
-- reg_unb_sens_miso => reg_unb_sens_miso,
-- reg_ppsh_mosi => reg_ppsh_mosi,
-- reg_ppsh_miso => reg_ppsh_miso,
-- eth1g_mm_rst => eth1g_mm_rst,
-- eth1g_reg_interrupt => eth1g_reg_interrupt,
-- eth1g_ram_mosi => eth1g_ram_mosi,
-- eth1g_ram_miso => eth1g_ram_miso,
-- eth1g_reg_mosi => eth1g_reg_mosi,
-- eth1g_reg_miso => eth1g_reg_miso,
-- eth1g_tse_mosi => eth1g_tse_mosi,
-- eth1g_tse_miso => eth1g_tse_miso,
-- reg_diag_bg_input_mosi => reg_diag_bg_input_mosi,
-- reg_diag_bg_input_miso => reg_diag_bg_input_miso,
-- reg_diag_bg_mesh_mosi => reg_diag_bg_mesh_mosi,
-- reg_diag_bg_mesh_miso => reg_diag_bg_mesh_miso,
-- ram_diag_bg_mesh_mosi => ram_diag_bg_mesh_mosi,
-- ram_diag_bg_mesh_miso => ram_diag_bg_mesh_miso,
-- reg_diagnostics_mosi => reg_diagnostics_mosi,
-- reg_diagnostics_miso => reg_diagnostics_miso,
-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
-- reg_diag_data_buf_input_mosi => reg_diag_data_buf_input_mosi,
-- reg_diag_data_buf_input_miso => reg_diag_data_buf_input_miso,
-- ram_diag_data_buf_input_mosi => ram_diag_data_buf_input_mosi,
-- ram_diag_data_buf_input_miso => ram_diag_data_buf_input_miso,
-- reg_diag_data_buf_mesh_mosi => reg_diag_data_buf_mesh_mosi,
-- reg_diag_data_buf_mesh_miso => reg_diag_data_buf_mesh_miso,
-- ram_diag_data_buf_mesh_mosi => ram_diag_data_buf_mesh_mosi,
-- ram_diag_data_buf_mesh_miso => ram_diag_data_buf_mesh_miso,
-- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
-- ram_fil_coefs_miso => ram_fil_coefs_miso,
-- reg_mdio_0_mosi => reg_mdio_0_mosi,
-- reg_mdio_0_miso => reg_mdio_0_miso,
-- reg_mdio_1_mosi => reg_mdio_1_mosi,
-- reg_mdio_1_miso => reg_mdio_1_miso,
-- reg_mdio_2_mosi => reg_mdio_2_mosi,
-- reg_mdio_2_miso => reg_mdio_2_miso,
-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
-- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
-- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
-- reg_tr_xaui_miso => reg_tr_xaui_miso,
-- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
-- reg_bsn_monitor_miso => reg_bsn_monitor_miso
-- );
--
-- SIGNAL reg_wdi_mosi : t_mem_mosi;
-- SIGNAL reg_wdi_miso : t_mem_miso;
-- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
-- SIGNAL reg_unb_system_info_miso : t_mem_miso;
-- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
-- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
-- SIGNAL reg_unb_sens_miso : t_mem_miso;
-- SIGNAL reg_ppsh_mosi : t_mem_mosi;
-- SIGNAL reg_ppsh_miso : t_mem_miso;
-- SIGNAL eth1g_ram_mosi : t_mem_mosi;
-- SIGNAL eth1g_ram_miso : t_mem_miso;
-- SIGNAL eth1g_reg_mosi : t_mem_mosi;
-- SIGNAL eth1g_reg_miso : t_mem_miso;
-- SIGNAL eth1g_tse_mosi : t_mem_mosi;
-- SIGNAL eth1g_tse_miso : t_mem_miso;
-- SIGNAL reg_diag_bg_input_mosi : t_mem_mosi;
-- SIGNAL reg_diag_bg_input_miso : t_mem_miso;
-- SIGNAL reg_diag_bg_mesh_mosi : t_mem_mosi;
-- SIGNAL reg_diag_bg_mesh_miso : t_mem_miso;
-- SIGNAL ram_diag_bg_mesh_mosi : t_mem_mosi;
-- SIGNAL ram_diag_bg_mesh_miso : t_mem_miso;
-- SIGNAL reg_diagnostics_mosi : t_mem_mosi;
-- SIGNAL reg_diagnostics_miso : t_mem_miso;
-- SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
-- SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
-- SIGNAL reg_diag_data_buf_input_mosi : t_mem_mosi;
-- SIGNAL reg_diag_data_buf_input_miso : t_mem_miso;
-- SIGNAL ram_diag_data_buf_input_mosi : t_mem_mosi;
-- SIGNAL ram_diag_data_buf_input_miso : t_mem_miso;
-- SIGNAL reg_diag_data_buf_mesh_mosi : t_mem_mosi;
-- SIGNAL reg_diag_data_buf_mesh_miso : t_mem_miso;
-- SIGNAL ram_diag_data_buf_mesh_mosi : t_mem_mosi;
-- SIGNAL ram_diag_data_buf_mesh_miso : t_mem_miso;
-- SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
-- SIGNAL ram_fil_coefs_miso : t_mem_miso;
-- SIGNAL reg_mdio_0_mosi : t_mem_mosi;
-- SIGNAL reg_mdio_0_miso : t_mem_miso;
-- SIGNAL reg_mdio_1_mosi : t_mem_mosi;
-- SIGNAL reg_mdio_1_miso : t_mem_miso;
-- SIGNAL reg_mdio_2_mosi : t_mem_mosi;
-- SIGNAL reg_mdio_2_miso : t_mem_miso;
-- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
-- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
-- SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
-- SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
-- SIGNAL reg_tr_10gbe_miso : t_mem_miso;
-- SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
-- SIGNAL reg_tr_xaui_miso : t_mem_miso;
-- SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
-- SIGNAL reg_bsn_monitor_miso : t_mem_miso;
--
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
ENTITY mmm_apertif_unb1_correlator IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim : BOOLEAN := FALSE;
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_wpfb : t_wpfb;
g_hdr_field_arr : t_common_field_arr;
g_use_qsys : BOOLEAN := TRUE
g_sim_node_nr : NATURAL := 0
);
PORT (
xo_clk : IN STD_LOGIC;
xo_rst_n : IN STD_LOGIC;
xo_rst : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
mm_clk : OUT STD_LOGIC;
mm_locked : OUT STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
mm_clk : IN STD_LOGIC := '1';
mm_rst : IN STD_LOGIC := '1';
pout_wdi : OUT STD_LOGIC := '1';
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
-- system_info
reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
reg_unb_system_info_mosi : OUT t_mem_mosi;
reg_unb_system_info_miso : IN t_mem_miso;
reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
-- UniBoard I2C sensors
rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso;
-- PPSH
reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
-- Block generator
reg_diag_bg_mosi : OUT t_mem_mosi;
reg_diag_bg_miso : IN t_mem_miso;
-- DP Offload RX
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso;
-- 10 GbE
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso;
reg_tr_xaui_mosi : OUT t_mem_mosi;
reg_tr_xaui_miso : IN t_mem_miso;
reg_mdio_mosi_arr : OUT t_mem_mosi_arr(3-1 DOWNTO 0);
reg_mdio_miso_arr : IN t_mem_miso_arr(3-1 DOWNTO 0);
-- BSN monitors
reg_bsn_monitor_mosi : OUT t_mem_mosi;
reg_bsn_monitor_miso : IN t_mem_miso;
-- Data buffers
reg_diag_data_buf_mosi : OUT t_mem_mosi;
reg_diag_data_buf_miso : IN t_mem_miso;
ram_diag_data_buf_mosi : OUT t_mem_mosi;
ram_diag_data_buf_miso : IN t_mem_miso;
-- Filter coefficients
ram_fil_coefs_mosi : OUT t_mem_mosi;
ram_fil_coefs_miso : IN t_mem_miso;
-- 1GbE visibility Offload TX
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
-- eth1g
eth1g_tse_clk : OUT STD_LOGIC;
reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso;
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso
eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diag_bg_input_mosi : OUT t_mem_mosi;
reg_diag_bg_input_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diag_bg_mesh_mosi : OUT t_mem_mosi;
reg_diag_bg_mesh_miso : IN t_mem_miso := c_mem_miso_rst;
ram_diag_bg_mesh_mosi : OUT t_mem_mosi;
ram_diag_bg_mesh_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diagnostics_mosi : OUT t_mem_mosi;
reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_nonbonded_mosi : OUT t_mem_mosi;
reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diag_data_buf_input_mosi : OUT t_mem_mosi;
reg_diag_data_buf_input_miso : IN t_mem_miso := c_mem_miso_rst;
ram_diag_data_buf_input_mosi : OUT t_mem_mosi;
ram_diag_data_buf_input_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diag_data_buf_mesh_mosi : OUT t_mem_mosi;
reg_diag_data_buf_mesh_miso : IN t_mem_miso := c_mem_miso_rst;
ram_diag_data_buf_mesh_mosi : OUT t_mem_mosi;
ram_diag_data_buf_mesh_miso : IN t_mem_miso := c_mem_miso_rst;
ram_fil_coefs_mosi : OUT t_mem_mosi;
ram_fil_coefs_miso : IN t_mem_miso := c_mem_miso_rst;
reg_mdio_0_mosi : OUT t_mem_mosi;
reg_mdio_0_miso : IN t_mem_miso := c_mem_miso_rst;
reg_mdio_1_mosi : OUT t_mem_mosi;
reg_mdio_1_miso : IN t_mem_miso := c_mem_miso_rst;
reg_mdio_2_mosi : OUT t_mem_mosi;
reg_mdio_2_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_10gbe_mosi : OUT t_mem_mosi;
reg_tr_10gbe_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_xaui_mosi : OUT t_mem_mosi;
reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
reg_bsn_monitor_mosi : OUT t_mem_mosi;
reg_bsn_monitor_miso : IN t_mem_miso := c_mem_miso_rst
);
END mmm_apertif_unb1_correlator;
END ENTITY mmm_apertif_unb1_correlator;
ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
CONSTANT c_nof_inputs : NATURAL := 3;
-- tr_xaui
CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
CONSTANT c_reg_tr_xaui_addr_w : NATURAL := ceil_log2(c_max_nof_xaui_inst* pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
-- dp_offload_rx
CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(c_nof_inputs* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
-- tr_10GbE
CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
CONSTANT c_reg_tr_10GbE_multi_adr_w : NATURAL := ceil_log2(c_nof_inputs* pow2(c_reg_tr_10GbE_adr_w));
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_adr_w : NATURAL := ceil_log2((c_nof_inputs+1+1)* pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_ram_diag_data_buf_addr_w : NATURAL := 17; -- 12 streams*8192 buffer words = 98kWords -> 2^17=128kWords
-- 1GbE Visibility offload TX
CONSTANT c_nof_header_fields : NATURAL := 34+3; -- 34 fields but 3 fields (MACs and timestamp) occupy an extra 32b register word
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := c_nof_header_fields;
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
-- ( 64 * 8 / 1 )
CONSTANT c_ram_fil_coefs_addr_w : natural := ceil_log2(g_wpfb.nof_points * g_wpfb.nof_taps / g_wpfb.wb_factor);
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_tse_clk_period : TIME := 8 ns;
CONSTANT c_sim_node_type : STRING(1 TO 2) := sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
SIGNAL i_mm_clk : STD_LOGIC := '1';
SIGNAL i_tse_clk : STD_LOGIC := '1';
CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC ;
SIGNAL sim_eth_psc_access : STD_LOGIC ;
SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_eth1g_reg_miso : t_mem_miso;
SIGNAL mm_rst_n : STD_LOGIC ;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
COMPONENT mm_file
COMPONENT mm_file IS
GENERIC (
g_file_prefix : STRING ;
g_mm_clk_period : TIME := c_mm_clk_period;
g_mm_clk_period : TIME := 8 ns;
g_update_on_change : BOOLEAN := FALSE;
g_mm_rd_latency : NATURAL := 1
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
mm_master_in : IN t_mem_miso := c_mem_miso_rst
);
END COMPONENT;
END COMPONENT mm_file;
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-- . Note the SLV->SL edits, e.g. coe_address_export_from_the_reg_wdi.
-----------------------------------------------------------------------------
component qsys_apertif_unb1_correlator is
port (
mm_clk : out std_logic; -- clk
out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0); -- export
out_port_from_the_pio_wdi : out std_logic; -- export
COMPONENT qsys_apertif_unb1_correlator IS
PORT (
ram_diag_data_buf_mesh_address_export : out std_logic_vector(5 downto 0);
reg_diag_data_buf_input_reset_export : out std_logic;
reg_dp_offload_tx_hdr_dat_write_export : out std_logic;
reg_diag_data_buf_input_clk_export : out std_logic;
eth1g_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
ram_diag_data_buf_mesh_clk_export : out std_logic;
reg_diag_data_buf_input_write_export : out std_logic;
ram_diag_data_buf_mesh_writedata_export : out std_logic_vector(31 downto 0);
reset_in_reset_n : in std_logic := '0';
reg_diagnostics_write_export : out std_logic;
pio_pps_address_export : out std_logic;
pio_system_info_address_export : out std_logic_vector(4 downto 0);
ram_diag_data_buf_input_reset_export : out std_logic;
pio_pps_reset_export : out std_logic;
eth1g_tse_writedata_export : out std_logic_vector(31 downto 0);
reg_mdio_1_clk_export : out std_logic;
reg_tr_10gbe_write_export : out std_logic;
reg_diag_bg_mesh_read_export : out std_logic;
reg_diag_data_buf_mesh_writedata_export : out std_logic_vector(31 downto 0);
ram_diag_bg_mesh_clk_export : out std_logic;
eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_diag_bg_mesh_reset_export : out std_logic;
ram_fil_coefs_clk_export : out std_logic;
reg_mdio_0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_ram_address_export : out std_logic_vector(9 downto 0);
pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_dp_offload_rx_hdr_dat_clk_export : out std_logic;
reg_diag_data_buf_mesh_write_export : out std_logic;
reg_diag_data_buf_mesh_reset_export : out std_logic;
pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
eth1g_reg_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_mesh_address_export : out std_logic_vector(2 downto 0);
ram_diag_bg_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_unb_sens_reset_export : out std_logic;
reg_tr_xaui_write_export : out std_logic;
eth1g_tse_address_export : out std_logic_vector(9 downto 0);
reg_wdi_reset_export : out std_logic;
reg_tr_xaui_writedata_export : out std_logic_vector(31 downto 0);
clk_in_clk : in std_logic := '0';
rom_system_info_clk_export : out std_logic;
reg_unb_sens_read_export : out std_logic;
reg_unb_sens_write_export : out std_logic;
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_0_clk_export : out std_logic;
eth1g_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_ram_write_export : out std_logic;
reg_diagnostics_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_data_buf_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0);
reg_tr_nonbonded_clk_export : out std_logic;
reg_tr_xaui_address_export : out std_logic_vector(10 downto 0);
reg_unb_sens_clk_export : out std_logic;
reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
reg_mdio_0_write_export : out std_logic;
ram_diag_bg_mesh_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_input_write_export : out std_logic;
reg_dp_offload_rx_hdr_dat_write_export : out std_logic;
eth1g_ram_read_export : out std_logic;
reg_wdi_read_export : out std_logic;
reg_dp_offload_rx_hdr_dat_read_export : out std_logic;
eth1g_reg_read_export : out std_logic;
ram_diag_data_buf_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_tr_10gbe_read_export : out std_logic;
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic;
reg_bsn_monitor_reset_export : out std_logic;
eth1g_tse_write_export : out std_logic;
reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_bsn_monitor_write_export : out std_logic;
reg_mdio_2_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_tr_xaui_waitrequest_export : in std_logic := '0';
reg_diag_data_buf_input_writedata_export : out std_logic_vector(31 downto 0);
pio_pps_clk_export : out std_logic;
eth1g_reg_address_export : out std_logic_vector(3 downto 0);
reg_diag_data_buf_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_tr_xaui_reset_export : out std_logic;
rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic;
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0);
ram_diag_data_buf_input_address_export : out std_logic_vector(16 downto 0);
reg_tr_nonbonded_reset_export : out std_logic;
reg_mdio_2_read_export : out std_logic;
reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_mesh_write_export : out std_logic;
reg_bsn_monitor_read_export : out std_logic;
reg_mdio_2_reset_export : out std_logic;
reg_tr_nonbonded_address_export : out std_logic_vector(3 downto 0);
reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_input_writedata_export : out std_logic_vector(31 downto 0);
ram_diag_data_buf_input_write_export : out std_logic;
reg_wdi_address_export : out std_logic;
pio_system_info_write_export : out std_logic;
reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
ram_fil_coefs_address_export : out std_logic_vector(8 downto 0);
reg_tr_nonbonded_writedata_export : out std_logic_vector(31 downto 0);
reg_tr_nonbonded_write_export : out std_logic;
pio_pps_write_export : out std_logic;
rom_system_info_write_export : out std_logic;
ram_diag_data_buf_input_read_export : out std_logic;
reg_diag_bg_input_clk_export : out std_logic;
rom_system_info_read_export : out std_logic;
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic;
reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(6 downto 0);
reg_diagnostics_address_export : out std_logic_vector(5 downto 0);
reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
ram_diag_data_buf_mesh_reset_export : out std_logic;
reg_mdio_2_clk_export : out std_logic;
reg_tr_nonbonded_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_mdio_2_address_export : out std_logic_vector(2 downto 0);
reg_diag_data_buf_mesh_address_export : out std_logic;
ram_diag_data_buf_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_tse_read_export : out std_logic;
reg_diag_bg_mesh_clk_export : out std_logic;
reg_tr_xaui_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
reg_mdio_1_read_export : out std_logic;
eth1g_ram_writedata_export : out std_logic_vector(31 downto 0);
ram_diag_data_buf_mesh_write_export : out std_logic;
ram_fil_coefs_reset_export : out std_logic;
reg_mdio_2_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_bg_input_address_export : out std_logic_vector(2 downto 0);
reg_tr_nonbonded_read_export : out std_logic;
out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0);
reg_mdio_1_address_export : out std_logic_vector(2 downto 0);
reg_tr_xaui_read_export : out std_logic;
reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
pio_system_info_reset_export : out std_logic;
reg_diag_data_buf_input_read_export : out std_logic;
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0);
pio_system_info_read_export : out std_logic;
ram_diag_bg_mesh_reset_export : out std_logic;
ram_fil_coefs_write_export : out std_logic;
reg_bsn_monitor_address_export : out std_logic_vector(6 downto 0);
reg_mdio_1_reset_export : out std_logic;
ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_wdi_clk_export : out std_logic;
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_diag_bg_mesh_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_mm_rst_export : out std_logic;
reg_diagnostics_read_export : out std_logic;
ram_fil_coefs_read_export : out std_logic;
reg_tr_10gbe_reset_export : out std_logic;
reg_diag_data_buf_mesh_clk_export : out std_logic;
reg_diagnostics_reset_export : out std_logic;
reg_tr_10gbe_clk_export : out std_logic;
out_port_from_the_pio_wdi : out std_logic;
reg_bsn_monitor_clk_export : out std_logic;
eth1g_reg_write_export : out std_logic;
reg_mdio_1_write_export : out std_logic;
reg_diag_bg_input_read_export : out std_logic;
reg_dp_offload_tx_hdr_dat_read_export : out std_logic;
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
ram_diag_data_buf_input_clk_export : out std_logic;
reg_diag_data_buf_mesh_read_export : out std_logic;
reg_wdi_write_export : out std_logic;
reg_tr_xaui_clk_export : out std_logic;
reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
pio_pps_read_export : out std_logic;
reg_mdio_2_write_export : out std_logic;
pio_system_info_clk_export : out std_logic;
ram_diag_bg_mesh_read_export : out std_logic;
reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0);
ram_diag_bg_mesh_address_export : out std_logic_vector(9 downto 0);
pio_pps_writedata_export : out std_logic_vector(31 downto 0);
eth1g_tse_waitrequest_export : in std_logic := '0';
reg_mdio_0_writedata_export : out std_logic_vector(31 downto 0);
reg_tr_10gbe_waitrequest_export : in std_logic := '0';
reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
eth1g_mm_clk_export : out std_logic;
reg_diag_bg_input_reset_export : out std_logic;
rom_system_info_reset_export : out std_logic;
ram_diag_bg_mesh_write_export : out std_logic;
ram_diag_data_buf_input_writedata_export : out std_logic_vector(31 downto 0);
reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
reg_mdio_0_reset_export : out std_logic;
ram_diag_data_buf_mesh_read_export : out std_logic;
rom_system_info_address_export : out std_logic_vector(9 downto 0);
reg_diag_bg_mesh_writedata_export : out std_logic_vector(31 downto 0);
reg_diag_data_buf_input_address_export : out std_logic;
eth1g_irq_export : in std_logic := '0';
reg_mdio_0_address_export : out std_logic_vector(2 downto 0);
reg_diag_bg_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_diagnostics_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
reg_diagnostics_clk_export : out std_logic;
reg_mdio_0_read_export : out std_logic
);
END COMPONENT qsys_apertif_unb1_correlator;
reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_bg_read_export : out std_logic; -- export
reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_bg_write_export : out std_logic; -- export
reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_bg_clk_export : out std_logic; -- export
reg_diag_bg_reset_export : out std_logic; -- export
ram_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_data_buf_read_export : out std_logic; -- export
ram_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buf_write_export : out std_logic; -- export
ram_diag_data_buf_address_export : out std_logic_vector(16 downto 0); -- export
ram_diag_data_buf_clk_export : out std_logic; -- export
ram_diag_data_buf_reset_export : out std_logic; -- export
reg_diag_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_data_buf_read_export : out std_logic; -- export
reg_diag_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buf_write_export : out std_logic; -- export
reg_diag_data_buf_address_export : out std_logic;--_vector;(0 downto 0); -- export
reg_diag_data_buf_clk_export : out std_logic; -- export
reg_diag_data_buf_reset_export : out std_logic; -- export
ram_fil_coefs_reset_export : out std_logic; -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_address_export : out std_logic_vector(8 downto 0); -- export
ram_fil_coefs_write_export : out std_logic; -- export
ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_fil_coefs_read_export : out std_logic; -- export
ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mdio_0_reset_export : out std_logic; -- export
reg_mdio_0_clk_export : out std_logic; -- export
reg_mdio_0_address_export : out std_logic_vector(2 downto 0); -- export
reg_mdio_0_write_export : out std_logic; -- export
reg_mdio_0_read_export : out std_logic; -- export
reg_mdio_0_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mdio_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mdio_1_reset_export : out std_logic; -- export
reg_mdio_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_mdio_1_clk_export : out std_logic; -- export
reg_mdio_1_address_export : out std_logic_vector(2 downto 0); -- export
reg_mdio_1_write_export : out std_logic; -- export
reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mdio_1_read_export : out std_logic; -- export
reg_mdio_2_reset_export : out std_logic; -- export
reg_mdio_2_clk_export : out std_logic; -- export
reg_mdio_2_address_export : out std_logic_vector(2 downto 0); -- export
reg_mdio_2_write_export : out std_logic; -- export
reg_mdio_2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_mdio_2_read_export : out std_logic; -- export
reg_mdio_2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_rx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
reg_dp_offload_rx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_rx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
eth1g_mm_rst_export : out std_logic; -- export
eth1g_mm_clk_export : out std_logic; -- export
eth1g_tse_address_export : out std_logic_vector(9 downto 0); -- export
eth1g_tse_write_export : out std_logic; -- export
eth1g_tse_read_export : out std_logic; -- export
eth1g_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
eth1g_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
eth1g_tse_waitrequest_export : in std_logic := 'X'; -- export
eth1g_reg_address_export : out std_logic_vector(3 downto 0); -- export
eth1g_reg_write_export : out std_logic; -- export
eth1g_reg_read_export : out std_logic; -- export
eth1g_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
eth1g_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
eth1g_ram_address_export : out std_logic_vector(9 downto 0); -- export
eth1g_ram_write_export : out std_logic; -- export
eth1g_ram_read_export : out std_logic; -- export
eth1g_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
eth1g_irq_export : in std_logic := 'X'; -- export
reg_dp_offload_tx_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_clk_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
reg_dp_offload_tx_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_unb_sens_reset_export : out std_logic; -- export
reg_unb_sens_clk_export : out std_logic; -- export
reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
reg_unb_sens_write_export : out std_logic; -- export
reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_unb_sens_read_export : out std_logic; -- export
reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio_system_info_reset_export : out std_logic; -- export
pio_system_info_clk_export : out std_logic; -- export
pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
pio_system_info_write_export : out std_logic; -- export
pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_system_info_read_export : out std_logic; -- export
pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
pio_pps_reset_export : out std_logic; -- export
pio_pps_clk_export : out std_logic; -- export
pio_pps_address_export : out std_logic;--_vector(0 downto 0); -- export
pio_pps_write_export : out std_logic; -- export
pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_pps_read_export : out std_logic; -- export
pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_wdi_reset_export : out std_logic; -- export
reg_wdi_clk_export : out std_logic; -- export
reg_wdi_address_export : out std_logic;--_vector(0 downto 0); -- export
reg_wdi_write_export : out std_logic; -- export
reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_wdi_read_export : out std_logic; -- export
reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_clk_export : out std_logic; -- export
rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
rom_system_info_write_export : out std_logic; -- export
rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
rom_system_info_read_export : out std_logic; -- export
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
epcs_clk : out std_logic; -- clk
tse_clk : out std_logic; -- clk
altpll_0_c3_clk : out std_logic; -- clk
altpll_0_areset_export : in std_logic := 'X'; -- export
altpll_0_locked_export : out std_logic; -- export
altpll_0_phasedone_export : out std_logic; -- export
reg_tr_10gbe_reset_export : out std_logic; -- export
reg_tr_10gbe_clk_export : out std_logic; -- export
reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0); -- export
reg_tr_10gbe_write_export : out std_logic; -- export
reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_10gbe_read_export : out std_logic; -- export
reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_tr_10gbe_waitrequest_export : in std_logic := 'X'; -- export
reg_tr_xaui_reset_export : out std_logic; -- export
reg_tr_xaui_clk_export : out std_logic; -- export
reg_tr_xaui_address_export : out std_logic_vector(10 downto 0); -- export
reg_tr_xaui_write_export : out std_logic; -- export
reg_tr_xaui_read_export : out std_logic; -- export
reg_tr_xaui_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_tr_xaui_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_tr_xaui_waitrequest_export : in std_logic := 'X'; -- export
reg_bsn_monitor_reset_export : out std_logic; -- export
reg_bsn_monitor_clk_export : out std_logic; -- export
reg_bsn_monitor_address_export : out std_logic_vector(6 downto 0); -- export
reg_bsn_monitor_write_export : out std_logic; -- export
reg_bsn_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_read_export : out std_logic; -- export
reg_bsn_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
clk_in_clk : in std_logic := 'X'; -- clk
reset_in_reset_n : in std_logic := 'X' -- reset_n
);
end component qsys_apertif_unb1_correlator;
BEGIN
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
i_tse_clk <= NOT i_tse_clk AFTER c_tse_clk_period/2;
mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
eth1g_mm_rst <= '1', '0' AFTER c_tse_clk_period*5;
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_eth1g_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
PORT MAP(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
u_mm_file_eth1g_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
u_mm_file_reg_diag_bg_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_INPUT")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_input_mosi, reg_diag_bg_input_miso );
u_mm_file_reg_diag_bg_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_MESH")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mesh_mosi, reg_diag_bg_mesh_miso );
u_mm_file_ram_diag_bg_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_MESH")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mesh_mosi, ram_diag_bg_mesh_miso );
u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
u_mm_file_reg_diag_data_buf_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_INPUT")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_input_mosi, reg_diag_data_buf_input_miso );
u_mm_file_ram_diag_data_buf_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_INPUT")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_input_mosi, ram_diag_data_buf_input_miso );
u_mm_file_reg_diag_data_buf_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_MESH")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mesh_mosi, reg_diag_data_buf_mesh_miso );
u_mm_file_ram_diag_data_buf_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_MESH")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mesh_mosi, ram_diag_data_buf_mesh_miso );
u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
u_mm_file_reg_mdio_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_0")
PORT MAP(mm_rst, mm_clk, reg_mdio_0_mosi, reg_mdio_0_miso );
u_mm_file_reg_mdio_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_1")
PORT MAP(mm_rst, mm_clk, reg_mdio_1_mosi, reg_mdio_1_miso );
u_mm_file_reg_mdio_2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_2")
PORT MAP(mm_rst, mm_clk, reg_mdio_2_mosi, reg_mdio_2_miso );
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
PORT MAP(mm_rst, i_mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
u_mm_file_reg_tr_10gbe : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
PORT MAP(mm_rst, mm_clk, reg_tr_10gbe_mosi, reg_tr_10gbe_miso );
u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
p_eth_setup : PROCESS
BEGIN
sim_eth_mm_bus_switch <= '1';
eth1g_tse_mosi.wr <= '0';
eth1g_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(i_mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
WAIT UNTIL rising_edge(mm_clk);
proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
END PROCESS;
......@@ -421,7 +528,6 @@ BEGIN
eth1g_reg_mosi <= i_eth1g_reg_mosi;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
......@@ -429,385 +535,202 @@ BEGIN
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
END GENERATE;
----------------------------------------------------------------------------
-- SOPC or QSYS for synthesis
----------------------------------------------------------------------------
gen_mmm_apertif_unb1_correlator : IF g_sim = FALSE GENERATE
gen_qsys : IF g_use_qsys = TRUE GENERATE
u_qsys_apertif_unb1_correlator : qsys_apertif_unb1_correlator
PORT MAP (
clk_in_clk => xo_clk,
reset_in_reset_n => xo_rst_n,
mm_clk => i_mm_clk,
tse_clk => i_tse_clk,
gen_qsys_apertif_unb1_correlator : IF g_sim = FALSE GENERATE
-- the_altpll_0
altpll_0_locked_export => mm_locked,
altpll_0_phasedone_export => OPEN,
altpll_0_areset_export => xo_rst,
mm_rst_n <= NOT(mm_rst);
-- the_avs_eth_0
u_qsys_apertif_unb1_correlator : qsys_apertif_unb1_correlator
PORT MAP(
clk_in_clk => mm_clk,
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_mm_clk_export => OPEN,
eth1g_mm_rst_export => eth1g_mm_rst,
eth1g_tse_address_export => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
eth1g_tse_write_export => eth1g_tse_mosi.wr,
eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_ram_address_export => eth1g_ram_mosi.address(9 DOWNTO 0),
eth1g_ram_read_export => eth1g_ram_mosi.rd,
eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
eth1g_ram_write_export => eth1g_ram_mosi.wr,
eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_reg_address_export => eth1g_reg_mosi.address(3 DOWNTO 0),
eth1g_reg_read_export => eth1g_reg_mosi.rd,
eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
eth1g_reg_write_export => eth1g_reg_mosi.wr,
eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_tse_address_export => eth1g_tse_mosi.address(9 DOWNTO 0),
eth1g_tse_read_export => eth1g_tse_mosi.rd,
eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
eth1g_reg_address_export => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
eth1g_reg_write_export => eth1g_reg_mosi.wr,
eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_reg_read_export => eth1g_reg_mosi.rd,
eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_ram_address_export => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
eth1g_ram_write_export => eth1g_ram_mosi.wr,
eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
eth1g_ram_read_export => eth1g_ram_mosi.rd,
eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-- the_reg_unb_sens
reg_unb_sens_clk_export => OPEN,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
eth1g_tse_write_export => eth1g_tse_mosi.wr,
eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
out_port_from_the_pio_debug_wave => OPEN,
-- the_pio_pps
out_port_from_the_pio_wdi => pout_wdi,
pio_pps_address_export => reg_ppsh_mosi.address(0),
pio_pps_clk_export => OPEN,
pio_pps_reset_export => OPEN,
pio_pps_address_export => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
pio_pps_read_export => reg_ppsh_mosi.rd,
pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_system_info: actually a avs_common_mm instance
pio_system_info_address_export => reg_unb_system_info_mosi.address(4 DOWNTO 0),
pio_system_info_clk_export => OPEN,
pio_system_info_reset_export => OPEN,
pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_rom_system_info
rom_system_info_clk_export => OPEN,
rom_system_info_reset_export => OPEN,
rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
out_port_from_the_pio_wdi => pout_wdi,
-- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
reg_wdi_clk_export => OPEN,
reg_wdi_reset_export => OPEN,
reg_wdi_address_export => reg_wdi_mosi.address(0),
reg_wdi_read_export => reg_wdi_mosi.rd,
reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_write_export => reg_wdi_mosi.wr,
reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_readdata_export => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_bg_read_export => reg_diag_bg_mosi.rd,
reg_diag_bg_writedata_export => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_write_export => reg_diag_bg_mosi.wr,
reg_diag_bg_address_export => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
reg_diag_bg_clk_export => OPEN,
reg_diag_bg_reset_export => OPEN,
ram_diag_data_buf_readdata_export => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_read_export => ram_diag_data_buf_mosi.rd,
ram_diag_data_buf_writedata_export => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_write_export => ram_diag_data_buf_mosi.wr,
ram_diag_data_buf_address_export => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_addr_w-1 DOWNTO 0),
ram_diag_data_buf_clk_export => OPEN,
ram_diag_data_buf_reset_export => OPEN,
reg_diag_data_buf_readdata_export => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_read_export => reg_diag_data_buf_mosi.rd,
reg_diag_data_buf_writedata_export => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_write_export => reg_diag_data_buf_mosi.wr,
reg_diag_data_buf_address_export => reg_diag_data_buf_mosi.address(0),
reg_diag_data_buf_clk_export => OPEN,
reg_diag_data_buf_reset_export => OPEN,
ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_ram_fil_coefs_addr_w-1 DOWNTO 0),
ram_diag_bg_mesh_address_export => ram_diag_bg_mesh_mosi.address(9 DOWNTO 0),
ram_diag_bg_mesh_clk_export => OPEN,
ram_diag_bg_mesh_read_export => ram_diag_bg_mesh_mosi.rd,
ram_diag_bg_mesh_readdata_export => ram_diag_bg_mesh_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_bg_mesh_reset_export => OPEN,
ram_diag_bg_mesh_write_export => ram_diag_bg_mesh_mosi.wr,
ram_diag_bg_mesh_writedata_export => ram_diag_bg_mesh_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_input_address_export => ram_diag_data_buf_input_mosi.address(16 DOWNTO 0),
ram_diag_data_buf_input_clk_export => OPEN,
ram_diag_data_buf_input_read_export => ram_diag_data_buf_input_mosi.rd,
ram_diag_data_buf_input_readdata_export => ram_diag_data_buf_input_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_input_reset_export => OPEN,
ram_diag_data_buf_input_write_export => ram_diag_data_buf_input_mosi.wr,
ram_diag_data_buf_input_writedata_export => ram_diag_data_buf_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_mesh_address_export => ram_diag_data_buf_mesh_mosi.address(5 DOWNTO 0),
ram_diag_data_buf_mesh_clk_export => OPEN,
ram_diag_data_buf_mesh_read_export => ram_diag_data_buf_mesh_mosi.rd,
ram_diag_data_buf_mesh_readdata_export => ram_diag_data_buf_mesh_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_mesh_reset_export => OPEN,
ram_diag_data_buf_mesh_write_export => ram_diag_data_buf_mesh_mosi.wr,
ram_diag_data_buf_mesh_writedata_export => ram_diag_data_buf_mesh_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(8 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_reset_export => OPEN,
-- the_reg_tr_10GbE
reg_tr_10gbe_clk_export => OPEN,
reg_tr_10gbe_reset_export => OPEN,
reg_tr_10gbe_address_export => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
reg_tr_10gbe_read_export => reg_tr_10GbE_mosi.rd,
reg_tr_10gbe_readdata_export => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_waitrequest_export => reg_tr_10GbE_miso.waitrequest,
reg_tr_10gbe_write_export => reg_tr_10GbE_mosi.wr,
reg_tr_10gbe_writedata_export => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_rx_hdr_dat
reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor
reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_address_export => reg_bsn_monitor_mosi.address(6 DOWNTO 0),
reg_bsn_monitor_clk_export => OPEN,
reg_bsn_monitor_read_export => reg_bsn_monitor_mosi.rd,
reg_bsn_monitor_readdata_export => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_reset_export => OPEN,
reg_bsn_monitor_write_export => reg_bsn_monitor_mosi.wr,
reg_bsn_monitor_writedata_export => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_hdr_dat
reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_adr_w-1 DOWNTO 0),
reg_diag_bg_input_address_export => reg_diag_bg_input_mosi.address(2 DOWNTO 0),
reg_diag_bg_input_clk_export => OPEN,
reg_diag_bg_input_read_export => reg_diag_bg_input_mosi.rd,
reg_diag_bg_input_readdata_export => reg_diag_bg_input_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_bg_input_reset_export => OPEN,
reg_diag_bg_input_write_export => reg_diag_bg_input_mosi.wr,
reg_diag_bg_input_writedata_export => reg_diag_bg_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_bg_mesh_address_export => reg_diag_bg_mesh_mosi.address(2 DOWNTO 0),
reg_diag_bg_mesh_clk_export => OPEN,
reg_diag_bg_mesh_read_export => reg_diag_bg_mesh_mosi.rd,
reg_diag_bg_mesh_readdata_export => reg_diag_bg_mesh_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_bg_mesh_reset_export => OPEN,
reg_diag_bg_mesh_write_export => reg_diag_bg_mesh_mosi.wr,
reg_diag_bg_mesh_writedata_export => reg_diag_bg_mesh_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_input_address_export => reg_diag_data_buf_input_mosi.address(0),
reg_diag_data_buf_input_clk_export => OPEN,
reg_diag_data_buf_input_read_export => reg_diag_data_buf_input_mosi.rd,
reg_diag_data_buf_input_readdata_export => reg_diag_data_buf_input_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_input_reset_export => OPEN,
reg_diag_data_buf_input_write_export => reg_diag_data_buf_input_mosi.wr,
reg_diag_data_buf_input_writedata_export => reg_diag_data_buf_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_mesh_address_export => reg_diag_data_buf_mesh_mosi.address(0),
reg_diag_data_buf_mesh_clk_export => OPEN,
reg_diag_data_buf_mesh_read_export => reg_diag_data_buf_mesh_mosi.rd,
reg_diag_data_buf_mesh_readdata_export => reg_diag_data_buf_mesh_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_mesh_reset_export => OPEN,
reg_diag_data_buf_mesh_write_export => reg_diag_data_buf_mesh_mosi.wr,
reg_diag_data_buf_mesh_writedata_export => reg_diag_data_buf_mesh_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diagnostics_address_export => reg_diagnostics_mosi.address(5 DOWNTO 0),
reg_diagnostics_clk_export => OPEN,
reg_diagnostics_read_export => reg_diagnostics_mosi.rd,
reg_diagnostics_readdata_export => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diagnostics_reset_export => OPEN,
reg_diagnostics_write_export => reg_diagnostics_mosi.wr,
reg_diagnostics_writedata_export => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(5 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_xaui
reg_tr_xaui_clk_export => OPEN,
reg_tr_xaui_reset_export => OPEN,
reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_0
reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 DOWNTO 0),
reg_mdio_0_clk_export => OPEN,
reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
reg_mdio_0_readdata_export => reg_mdio_0_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mdio_0_reset_export => OPEN,
reg_mdio_0_address_export => reg_mdio_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
reg_mdio_0_read_export => reg_mdio_mosi_arr(0).rd,
reg_mdio_0_readdata_export => reg_mdio_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
reg_mdio_0_write_export => reg_mdio_mosi_arr(0).wr,
reg_mdio_0_writedata_export => reg_mdio_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_1
reg_mdio_0_write_export => reg_mdio_0_mosi.wr,
reg_mdio_0_writedata_export => reg_mdio_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mdio_1_address_export => reg_mdio_1_mosi.address(2 DOWNTO 0),
reg_mdio_1_clk_export => OPEN,
reg_mdio_1_read_export => reg_mdio_1_mosi.rd,
reg_mdio_1_readdata_export => reg_mdio_1_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mdio_1_reset_export => OPEN,
reg_mdio_1_address_export => reg_mdio_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
reg_mdio_1_read_export => reg_mdio_mosi_arr(1).rd,
reg_mdio_1_readdata_export => reg_mdio_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
reg_mdio_1_write_export => reg_mdio_mosi_arr(1).wr,
reg_mdio_1_writedata_export => reg_mdio_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_2
reg_mdio_1_write_export => reg_mdio_1_mosi.wr,
reg_mdio_1_writedata_export => reg_mdio_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mdio_2_address_export => reg_mdio_2_mosi.address(2 DOWNTO 0),
reg_mdio_2_clk_export => OPEN,
reg_mdio_2_read_export => reg_mdio_2_mosi.rd,
reg_mdio_2_readdata_export => reg_mdio_2_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mdio_2_reset_export => OPEN,
reg_mdio_2_address_export => reg_mdio_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
reg_mdio_2_read_export => reg_mdio_mosi_arr(2).rd,
reg_mdio_2_readdata_export => reg_mdio_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
reg_mdio_2_write_export => reg_mdio_mosi_arr(2).wr,
reg_mdio_2_writedata_export => reg_mdio_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0)
reg_mdio_2_write_export => reg_mdio_2_mosi.wr,
reg_mdio_2_writedata_export => reg_mdio_2_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_address_export => reg_tr_10gbe_mosi.address(14 DOWNTO 0),
reg_tr_10gbe_clk_export => OPEN,
reg_tr_10gbe_read_export => reg_tr_10gbe_mosi.rd,
reg_tr_10gbe_readdata_export => reg_tr_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_10gbe_reset_export => OPEN,
reg_tr_10gbe_waitrequest_export => reg_tr_10gbe_miso.waitrequest,
reg_tr_10gbe_write_export => reg_tr_10gbe_mosi.wr,
reg_tr_10gbe_writedata_export => reg_tr_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tr_nonbonded_address_export => reg_tr_nonbonded_mosi.address(3 DOWNTO 0),
reg_tr_nonbonded_clk_export => OPEN,
reg_tr_nonbonded_read_export => reg_tr_nonbonded_mosi.rd,
reg_tr_nonbonded_readdata_export => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_nonbonded_reset_export => OPEN,
reg_tr_nonbonded_write_export => reg_tr_nonbonded_mosi.wr,
reg_tr_nonbonded_writedata_export => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(10 DOWNTO 0),
reg_tr_xaui_clk_export => OPEN,
reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
reg_tr_xaui_reset_export => OPEN,
reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 DOWNTO 0),
reg_unb_sens_clk_export => OPEN,
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_wdi_address_export => reg_wdi_mosi.address(0),
reg_wdi_clk_export => OPEN,
reg_wdi_read_export => reg_wdi_mosi.rd,
reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_write_export => reg_wdi_mosi.wr,
reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
reset_in_reset_n => mm_rst_n,
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
rom_system_info_clk_export => OPEN,
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
gen_sopc : IF g_use_qsys = FALSE GENERATE
u_sopc : ENTITY work.sopc_apertif_unb1_correlator
PORT MAP (
clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
reset_n => xo_rst_n,
mm_clk => i_mm_clk, -- 125 MHz system clock
tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
dp_clk => OPEN,
cal_reconf_clk => OPEN,
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-- the_reg_unb_sens
coe_clk_export_from_the_reg_unb_sens => OPEN,
coe_reset_export_from_the_reg_unb_sens => OPEN,
coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN,
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_rom_system_info
coe_clk_export_from_the_rom_system_info => OPEN,
coe_reset_export_from_the_rom_system_info => OPEN,
coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_wdi
out_port_from_the_pio_wdi => pout_wdi,
-- the_reg_wdi
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_0
coe_clk_export_from_the_reg_mdio_0 => OPEN,
coe_reset_export_from_the_reg_mdio_0 => OPEN,
coe_address_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).rd,
coe_readdata_export_to_the_reg_mdio_0 => reg_mdio_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wr,
coe_writedata_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_1
coe_clk_export_from_the_reg_mdio_1 => OPEN,
coe_reset_export_from_the_reg_mdio_1 => OPEN,
coe_address_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).rd,
coe_readdata_export_to_the_reg_mdio_1 => reg_mdio_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wr,
coe_writedata_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_mdio_2
coe_clk_export_from_the_reg_mdio_2 => OPEN,
coe_reset_export_from_the_reg_mdio_2 => OPEN,
coe_address_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).rd,
coe_readdata_export_to_the_reg_mdio_2 => reg_mdio_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wr,
coe_writedata_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_rx_hdr_dat
coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor
coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_bsn_monitor => OPEN,
coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_bsn_monitor => OPEN,
coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_10GbE
coe_clk_export_from_the_reg_tr_10GbE => OPEN,
coe_reset_export_from_the_reg_tr_10GbE => OPEN,
coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_multi_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.rd,
coe_readdata_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
coe_waitrequest_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.waitrequest,
coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_fil_coefs
coe_address_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.address(c_ram_fil_coefs_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_fil_coefs => OPEN,
coe_read_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.rd,
coe_readdata_export_to_the_ram_fil_coefs => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_fil_coefs => OPEN,
coe_write_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.wr,
coe_writedata_export_from_the_ram_fil_coefs => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buf
coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(9 DOWNTO 0),
coe_clk_export_from_the_ram_diag_data_buf => OPEN,
coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_diag_data_buf => OPEN,
coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_data_buf
coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(0),
coe_clk_export_from_the_reg_diag_data_buf => OPEN,
coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diag_data_buf => OPEN,
coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_xaui
coe_clk_export_from_the_reg_tr_xaui => OPEN,
coe_reset_export_from_the_reg_tr_xaui => OPEN,
coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END GENERATE;
END str;
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