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Commit a86676b8 authored by Pepping's avatar Pepping
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applications/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+ 81
− 109
View file @ a86676b8
...@@ -32,11 +32,13 @@ USE tse_lib.tse_pkg.ALL; ...@@ -32,11 +32,13 @@ USE tse_lib.tse_pkg.ALL;
USE tse_lib.eth_pkg.ALL; USE tse_lib.eth_pkg.ALL;
USE bf_lib.bf_pkg.ALL; USE bf_lib.bf_pkg.ALL;
ENTITY fn_bf IS ENTITY unb1_fn_bf IS
GENERIC ( GENERIC (
g_design_name : STRING := "unb1_fn_bf";
g_design_note : STRING := "UNUSED";
g_sim : BOOLEAN := FALSE; --Overridden by TB g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 4; g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
...@@ -64,19 +66,16 @@ ENTITY fn_bf IS ...@@ -64,19 +66,16 @@ ENTITY fn_bf IS
ETH_SGIN : IN STD_LOGIC; ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC ETH_SGOUT : OUT STD_LOGIC
); );
END fn_bf; END unb1_fn_bf;
ARCHITECTURE str OF fn_bf IS ARCHITECTURE str OF unb1_fn_bf IS
CONSTANT c_design_name : STRING := "fn_bf";
CONSTANT c_bf_offload : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port CONSTANT c_bf_offload : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port
CONSTANT c_use_phy : t_c_unb_use_phy := (1, 0, 0, 0, 0, 0, 0, 1); CONSTANT c_use_phy : t_c_unb_use_phy := (1, 0, 0, 0, 0, 0, 0, 1);
CONSTANT c_fw_version : t_unb_fw_version := (2, 3); -- firmware version x.y CONSTANT c_fw_version : t_unb_fw_version := (2, 3); -- firmware version x.y
CONSTANT c_nof_streams : NATURAL := c_eth_nof_udp_ports; CONSTANT c_nof_streams : NATURAL := c_eth_nof_udp_ports;
CONSTANT c_app_led_en : BOOLEAN := TRUE;
CONSTANT c_weights_write_only : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port. CONSTANT c_weights_write_only : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
-- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis -- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis
...@@ -106,7 +105,6 @@ ARCHITECTURE str OF fn_bf IS ...@@ -106,7 +105,6 @@ ARCHITECTURE str OF fn_bf IS
SIGNAL app_led_green : STD_LOGIC := '1'; SIGNAL app_led_green : STD_LOGIC := '1';
-- PIOs -- PIOs
SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL pout_wdi : STD_LOGIC; SIGNAL pout_wdi : STD_LOGIC;
-- WDI override -- WDI override
...@@ -186,70 +184,62 @@ BEGIN ...@@ -186,70 +184,62 @@ BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- General control function -- General control function
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_ctrl : ENTITY unb_common_lib.ctrl_unb_common u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP ( GENERIC MAP (
-- General
g_sim => g_sim, g_sim => g_sim,
g_design_name => c_design_name, g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date, g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time, g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn, g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version, g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb_mm_clk_freq_50M, g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_app_led_red => c_app_led_en,
g_app_led_green => c_app_led_en,
g_use_phy => c_use_phy, g_use_phy => c_use_phy,
g_udp_offload => sel_a_b(c_bf_offload, TRUE, FALSE), g_udp_offload => sel_a_b(c_bf_offload, TRUE, FALSE),
g_aux => c_unb1_board_aux,
g_udp_offload_nof_streams => c_nof_streams g_udp_offload_nof_streams => c_nof_streams
) )
PORT MAP ( PORT MAP (
-- -- Clock an reset signals
-- >>> SOPC system with conduit peripheral MM bus
--
-- System
cs_sim => cs_sim, cs_sim => cs_sim,
xo_clk => xo_clk, xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n, xo_rst_n => xo_rst_n,
mm_clk => mm_clk, mm_clk => mm_clk,
mm_locked => mm_locked, mm_locked => mm_locked,
mm_rst => mm_rst, mm_rst => mm_rst,
dp_rst => dp_rst, dp_rst => st_rst,
dp_clk => dp_clk, dp_clk => st_clk,
dp_pps => dp_pps, dp_pps => OPEN,
dp_rst_in => dp_rst, dp_rst_in => st_rst,
dp_clk_in => dp_clk, dp_clk_in => st_clk,
this_chip_id => OPEN, -- Toggle WDI
this_bck_id => OPEN,
app_led_red => app_led_red,
app_led_green => app_led_green,
-- PIOs
pout_debug_wave => pout_debug_wave,
pout_wdi => pout_wdi, pout_wdi => pout_wdi,
-- Manual WDI override -- MM buses
-- . Manual WDI override
reg_wdi_mosi => reg_wdi_mosi, reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso, reg_wdi_miso => reg_wdi_miso,
-- system_info -- . System_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi, reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso, reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi, rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso, rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors -- . UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi, reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso, reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH -- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi, reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso, reg_ppsh_miso => reg_ppsh_miso,
-- eth1g -- eth1g
eth1g_tse_clk => eth1g_tse_clk, eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_mm_rst => eth1g_mm_rst, eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi, eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso, eth1g_tse_miso => eth1g_tse_miso,
...@@ -263,30 +253,27 @@ BEGIN ...@@ -263,30 +253,27 @@ BEGIN
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr, udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_udp_tx_siso_arr, udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
-- -- FPGA pins
-- >>> Ctrl FPGA pins -- . General
--
-- General
CLK => CLK, CLK => CLK,
PPS => PPS, PPS => PPS,
WDI => WDI, WDI => WDI,
INTA => INTA, INTA => INTA,
INTB => INTB, INTB => INTB,
-- . Others
-- Others
VERSION => VERSION, VERSION => VERSION,
ID => ID, ID => ID,
TESTIO => TESTIO, TESTIO => TESTIO,
-- . I2C Interface to Sensors
-- I2C Interface to Sensors
sens_sc => sens_sc, sens_sc => sens_sc,
sens_sd => sens_sd, sens_sd => sens_sd,
-- . 1GbE Control Interface
ETH_clk => ETH_clk, ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN, ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT ETH_SGOUT => ETH_SGOUT
); );
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- MM master -- MM master
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -409,21 +396,6 @@ BEGIN ...@@ -409,21 +396,6 @@ BEGIN
bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr, bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
); );
-- Debug
gen_app_led : IF c_app_led_en=TRUE GENERATE
u_toggle : ENTITY common_lib.common_toggle
PORT MAP (
rst => dp_rst,
clk => dp_clk,
in_dat => beams_sosi_arr(0).sync,
in_val => beams_sosi_arr(0).valid,
out_dat => app_led_red
);
app_led_green <= beams_sosi_arr(0).valid;
END GENERATE;
END; END;
......
applications/unb1_fn_bf/src/vhdl/unb1_mmm_fn_bf.vhd 0 → 100644
+ 464
− 0
View file @ a86676b8
------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb_common_lib, mm_lib, tse_lib, bf_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb_common_lib.unb_common_pkg.ALL;
USE unb_common_lib.unb_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE tse_lib.tse_pkg.ALL;
USE tse_lib.tb_tse_pkg.ALL;
USE tse_lib.eth_pkg.ALL;
USE tse_lib.eth_layers_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
ENTITY mmm_fn_bf IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_bf : t_c_bf := c_bf
);
PORT (
xo_clk : IN STD_LOGIC;
xo_rst_n : IN STD_LOGIC;
xo_rst : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
mm_clk : OUT STD_LOGIC;
mm_locked : OUT STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
-- system_info
reg_unb_system_info_mosi : OUT t_mem_mosi;
reg_unb_system_info_miso : IN t_mem_miso;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
-- UniBoard I2C sensors
reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso;
-- Diagnostics
reg_diagnostics_mosi : OUT t_mem_mosi;
reg_diagnostics_miso : IN t_mem_miso;
-- Beamformer Node
-- . block generator
reg_diag_bg_mosi : OUT t_mem_mosi;
reg_diag_bg_miso : IN t_mem_miso;
ram_diag_bg_mosi : OUT t_mem_mosi;
ram_diag_bg_miso : IN t_mem_miso;
-- . beam former
ram_ss_ss_wide_mosi : OUT t_mem_mosi;
ram_ss_ss_wide_miso : IN t_mem_miso;
ram_bf_weights_mosi : OUT t_mem_mosi;
ram_bf_weights_miso : IN t_mem_miso;
ram_st_sst_bf_mosi : OUT t_mem_mosi;
ram_st_sst_bf_miso : IN t_mem_miso;
reg_st_sst_bf_mosi : OUT t_mem_mosi;
reg_st_sst_bf_miso : IN t_mem_miso;
-- dp_offload
reg_dp_ram_from_mm_mosi : OUT t_mem_mosi;
reg_dp_ram_from_mm_miso : IN t_mem_miso;
ram_dp_ram_from_mm_mosi : OUT t_mem_mosi;
ram_dp_ram_from_mm_miso : IN t_mem_miso;
-- . Nof words to offload selection
reg_dp_split_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_split_miso : IN t_mem_miso;
reg_dp_pkt_merge_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_pkt_merge_miso : IN t_mem_miso;
-- eth1g
eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso;
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso
);
END mmm_fn_bf;
ARCHITECTURE str OF mmm_fn_bf IS
-- Application specific constants (or generics)
CONSTANT c_bg_diag_wave_period : NATURAL := 4;
-- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
CONSTANT c_reg_diag_bg_addr_w : NATURAL := 3;
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams);
CONSTANT c_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_signal_paths*g_bf.nof_weights);
CONSTANT c_ram_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.stat_data_sz*g_bf.nof_weights*c_nof_complex);
CONSTANT c_reg_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2; -- 2 bits reserved for single reg_st_sst.
CONSTANT c_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths);
-- BF offload
CONSTANT c_hdr_nof_words : NATURAL := c_eth_total_header_nof_words;
CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_tse_data_w/c_word_w);
CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_dp_ram_mm_nof_words);
-- Simulation
CONSTANT c_mm_clk_period : TIME := 8 ns;
CONSTANT c_tse_clk_period : TIME := 8 ns;
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
SIGNAL i_mm_clk : STD_LOGIC := '1';
SIGNAL i_tse_clk : STD_LOGIC := '1';
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_mm_clk_period : TIME := c_mm_clk_period;
g_update_on_change : BOOLEAN := FALSE;
g_mm_rd_latency : NATURAL := 1
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
CONSTANT c_dut_src_mac : STD_LOGIC_VECTOR(c_eth_mac_slv'RANGE) := X"002286080001";
SIGNAL eth_psc_access : STD_LOGIC;
CONSTANT c_dut_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_reg_proc_mosi : t_mem_mosi;
SIGNAL eth1g_reg_proc_miso : t_mem_miso;
SIGNAL mm_bus_switch : STD_LOGIC;
BEGIN
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
i_tse_clk <= NOT i_tse_clk AFTER c_tse_clk_period/2;
eth1g_mm_rst <= '1', '0' AFTER c_tse_clk_period*5;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
PORT MAP(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
u_mm_file_ram_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
-- u_mm_file_ram_dp_ram_to_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_TO_MM")
-- PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_to_mm_mosi, ram_dp_ram_to_mm_miso );
u_mm_file_reg_dp_split : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
PORT MAP(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
u_mm_file_reg_dp_pkt_merge : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
PORT MAP(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
PORT MAP(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
u_mm_file_ram_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
PORT MAP(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
u_mm_file_reg_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
PORT MAP(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
p_eth_setup : PROCESS
BEGIN
mm_bus_switch <= '1';
eth1g_tse_mosi.wr <= '0';
eth1g_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
WAIT UNTIL rising_edge(i_mm_clk);
proc_tse_setup(FALSE, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tse_tx_ready_latency, c_dut_src_mac, eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_dut_control_rx_en, i_mm_clk, eth1g_reg_miso, eth1g_reg_proc_mosi); -- control rx en
mm_bus_switch <= '0';
WAIT;
END PROCESS;
p_switch : PROCESS(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
BEGIN
IF mm_bus_switch = '1' THEN
eth1g_reg_mosi <= eth1g_reg_proc_mosi;
ELSE
eth1g_reg_mosi <= i_eth1g_reg_mosi;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
END GENERATE;
-----------------------------------------------------------------------------
-- SOPC system
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- SOPC for synthesis
----------------------------------------------------------------------------
gen_sopc : IF g_sim = FALSE GENERATE
u_sopc : ENTITY work.sopc_fn_bf
PORT MAP (
-- 1) global signals:
clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
reset_n => xo_rst_n,
mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-- the_altpll_0
areset_to_the_altpll_0 => '0',
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tse_byte_addr_w-1 DOWNTO 0),
coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w-1 DOWNTO 0),
coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w-1 DOWNTO 0),
coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-- the_reg_unb_sens
coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_unb_sens => OPEN,
coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_unb_sens => OPEN,
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_st_sst
coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_st_sst => OPEN,
coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_st_sst => OPEN,
coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_st_sst
coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_st_sst => OPEN,
coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_st_sst => OPEN,
coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_ss_ss_wide
coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_bf_weights
coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_bf_weights => OPEN,
coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_bf_weights => OPEN,
coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bg_diag_bg
coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diag_bg => OPEN,
coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diag_bg => OPEN,
coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_bg
coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_diag_bg => OPEN,
coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_diag_bg => OPEN,
coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN,
-- the_pio_pps
coe_clk_export_from_the_pio_pps => OPEN,
coe_reset_export_from_the_pio_pps => OPEN,
coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb_mm_reg_default.reg_ppsh_adr_w-1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_rom_system_info
coe_clk_export_from_the_rom_system_info => OPEN,
coe_reset_export_from_the_rom_system_info => OPEN,
coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_wdi
out_port_from_the_pio_wdi => pout_wdi,
-- the_reg_wdi
coe_clk_export_from_the_reg_wdi => OPEN,
coe_reset_export_from_the_reg_wdi => OPEN,
coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_ram_from_mm
coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(0),
coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_dp_ram_from_mm
coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END;
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