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applications/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd

@@ -32,11 +32,13 @@ USE tse_lib.tse_pkg.ALL;
 USE tse_lib.eth_pkg.ALL;
 USE bf_lib.bf_pkg.ALL;
 
-ENTITY fn_bf IS
+ENTITY unb1_fn_bf IS
   GENERIC (
+    g_design_name : STRING  := "unb1_fn_bf";
+    g_design_note : STRING  := "UNUSED";
     g_sim         : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr  : NATURAL := 0;
-    g_sim_node_nr : NATURAL := 4;
+    g_sim_node_nr : NATURAL := 0;
     g_stamp_date  : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
     g_stamp_time  : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
     g_stamp_svn   : NATURAL := 0;  -- SVN revision    -- set by QSF
@@ -64,19 +66,16 @@ ENTITY fn_bf IS
     ETH_SGIN      : IN    STD_LOGIC;
     ETH_SGOUT     : OUT   STD_LOGIC
   );
-END fn_bf;
+END unb1_fn_bf;
 
 
-ARCHITECTURE str OF fn_bf IS   
+ARCHITECTURE str OF unb1_fn_bf IS   
 
   
-  CONSTANT c_design_name         : STRING  := "fn_bf";
   CONSTANT c_bf_offload            : BOOLEAN := FALSE; -- Offload BF out(0) datapath to 1GbE UDP TX port
   CONSTANT c_use_phy               : t_c_unb_use_phy := (1, 0, 0, 0, 0, 0, 0, 1); 
   CONSTANT c_fw_version            : t_unb_fw_version := (2, 3);  -- firmware version x.y
   CONSTANT c_nof_streams           : NATURAL := c_eth_nof_udp_ports;
-
-  CONSTANT c_app_led_en                : BOOLEAN := TRUE;
   CONSTANT c_weights_write_only    : BOOLEAN := TRUE; -- When set to TRUE the M9K blocks are forced to Simple Dual Port mode. When FALSE it is True Dual Port.
   
   -- Use default RAM inti files. The RAM init file for simulation lies one ../ level further way then for synthesis
@@ -106,7 +105,6 @@ ARCHITECTURE str OF fn_bf IS
   SIGNAL app_led_green              : STD_LOGIC := '1';
   
   -- PIOs
-  SIGNAL pout_debug_wave            : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL pout_wdi                   : STD_LOGIC;
 
   -- WDI override
@@ -186,70 +184,62 @@ BEGIN
   -----------------------------------------------------------------------------
   -- General control function
   -----------------------------------------------------------------------------
-  u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
+  u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
   GENERIC MAP (
-    -- General
     g_sim           => g_sim,
-    g_design_name   => c_design_name,
+    g_design_name   => g_design_name,
+    g_design_note   => g_design_note,
     g_stamp_date    => g_stamp_date,
     g_stamp_time    => g_stamp_time, 
     g_stamp_svn     => g_stamp_svn, 
     g_fw_version    => c_fw_version,
-    g_mm_clk_freq   => c_unb_mm_clk_freq_50M,
-    g_app_led_red   => c_app_led_en,
-    g_app_led_green => c_app_led_en,
+    g_mm_clk_freq   => c_unb1_board_mm_clk_freq_50M,
     g_use_phy       => c_use_phy,
     g_udp_offload   => sel_a_b(c_bf_offload, TRUE, FALSE),
+    g_aux           => c_unb1_board_aux,
     g_udp_offload_nof_streams => c_nof_streams
   )
   PORT MAP (
-    --
-    -- >>> SOPC system with conduit peripheral MM bus
-    --
-    -- System
+    -- Clock an reset signals
     cs_sim                   => cs_sim,
     xo_clk                   => xo_clk,
+    xo_rst                   => xo_rst,
     xo_rst_n                 => xo_rst_n,
+
     mm_clk                   => mm_clk,
     mm_locked                => mm_locked,
     mm_rst                   => mm_rst,
 
-    dp_rst                 => dp_rst,
-    dp_clk                 => dp_clk,
-    dp_pps                 => dp_pps,
-    dp_rst_in              => dp_rst,
-    dp_clk_in              => dp_clk,
+    dp_rst                   => st_rst,
+    dp_clk                   => st_clk,
+    dp_pps                   => OPEN,
+    dp_rst_in                => st_rst,
+    dp_clk_in                => st_clk,
     
-    this_chip_id           => OPEN,
-    this_bck_id            => OPEN,
-    
-    app_led_red            => app_led_red,
-    app_led_green          => app_led_green,
-    
-    -- PIOs
-    pout_debug_wave        => pout_debug_wave,
+    -- Toggle WDI
     pout_wdi                 => pout_wdi,
 
-    -- Manual WDI override
+    -- MM buses
+    -- . Manual WDI override
     reg_wdi_mosi             => reg_wdi_mosi,
     reg_wdi_miso             => reg_wdi_miso,
     
-    -- system_info
+    -- . System_info
     reg_unb_system_info_mosi => reg_unb_system_info_mosi,
     reg_unb_system_info_miso => reg_unb_system_info_miso, 
     rom_unb_system_info_mosi => rom_unb_system_info_mosi,
     rom_unb_system_info_miso => rom_unb_system_info_miso, 
     
-     -- UniBoard I2C sensors
+    -- . UniBoard I2C sensors
     reg_unb_sens_mosi        => reg_unb_sens_mosi,
     reg_unb_sens_miso        => reg_unb_sens_miso,    
     
-    -- PPSH
+    -- . PPSH
     reg_ppsh_mosi            => reg_ppsh_mosi,
     reg_ppsh_miso            => reg_ppsh_miso,
     
     -- eth1g
-    eth1g_tse_clk          => eth1g_tse_clk,
+    eth1g_tse_clk            => eth1g_tse_clk,   -- 125 MHz from xo_clk PLL in SOPC system
     eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
@@ -263,30 +253,27 @@ BEGIN
     udp_tx_sosi_arr        =>  eth1g_udp_tx_sosi_arr,
     udp_tx_siso_arr        =>  eth1g_udp_tx_siso_arr,
         
-    --
-    -- >>> Ctrl FPGA pins
-    --
-    -- General
+    -- FPGA pins
+    -- . General
     CLK                      => CLK,
     PPS                      => PPS,
     WDI                      => WDI,
     INTA                     => INTA,
     INTB                     => INTB,
-
-    -- Others
+    -- . Others
     VERSION                  => VERSION,
     ID                       => ID,
     TESTIO                   => TESTIO,
-    
-    -- I2C Interface to Sensors                        
+    -- . I2C Interface to Sensors
     sens_sc                  => sens_sc,
     sens_sd                  => sens_sd,        
-    
+    -- . 1GbE Control Interface
     ETH_clk                  => ETH_clk,
     ETH_SGIN                 => ETH_SGIN,
     ETH_SGOUT                => ETH_SGOUT
   );
   
+  
   -----------------------------------------------------------------------------
   -- MM master
   -----------------------------------------------------------------------------
@@ -409,21 +396,6 @@ BEGIN
     bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
     bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
   );
-  
-  -- Debug
-  gen_app_led : IF c_app_led_en=TRUE GENERATE
-    u_toggle : ENTITY common_lib.common_toggle
-    PORT MAP (
-      rst      => dp_rst,
-      clk      => dp_clk,
-      in_dat   => beams_sosi_arr(0).sync,
-      in_val   => beams_sosi_arr(0).valid,
-      out_dat  => app_led_red
-    );
-    
-    app_led_green <= beams_sosi_arr(0).valid;
-  END GENERATE;
-  
 END;