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Commit a75c21af authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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pinning design compiles with Q15.0

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with 293 additions and 149 deletions
boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
+ 6
− 4
View file @ a75c21af
......@@ -41,11 +41,10 @@ set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name TOP_LEVEL_ENTITY unb2_pinning
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45 MARCH 13, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
......@@ -1038,7 +1037,7 @@ set_location_assignment PIN_M16 -to MB_EVENT
#set_global_assignment -name DEVICE 10AX115U3F45I2LG
#set_global_assignment -name DEVICE 10AX115U4F45I3SGES
#set_global_assignment -name DEVICE 10AX115U4F45I2SGES
set_global_assignment -name DEVICE 10AX115U4F45I3SG
set_global_assignment -name DEVICE 10AX115U4F45I3SGES
......@@ -1664,4 +1663,7 @@ set_global_assignment -name SIP_FILE ../../src/ip/ddr4.sip
set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_pinning.vhd
set_global_assignment -name SOURCE_FILE db/unb2_pinning.cmp.rdb
set_global_assignment -name SDC_FILE ../../src/sdc/unb2_pinning.sdc
set_global_assignment -name QSYS_FILE ../../src/ip/system_fpll.qsys
set_instance_assignment -name UNFORCE_MERGE_PLL ON -to "*system_pll_altera_iopll_150*|altera_pll:altera_pll_i*|*"
set_global_assignment -name QSYS_FILE ../../src/ip/sys_clkctrl.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
+ 88
− 3
View file @ a75c21af
......@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -128,7 +129,7 @@
<module
name="ddr4_inst"
kind="altera_emif"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
......@@ -255,6 +256,7 @@
<parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
<parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
<parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
......@@ -299,15 +301,23 @@
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC" value="3" />
<parameter name="CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC" value="10" />
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
<parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
<parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
<parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
......@@ -316,33 +326,55 @@
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
<parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
<parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
<parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
<parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
<parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
<parameter name="DIAG_EXPORT_VJI" value="false" />
<parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
<parameter name="DIAG_EXTRA_CONFIGS" value="" />
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
<parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
<parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
<parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
<parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
<parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
<parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
<parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
<parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
<parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
......@@ -645,8 +677,10 @@
<parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -665,8 +699,10 @@
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -684,8 +720,10 @@
<parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -701,10 +739,13 @@
<parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
<parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -722,8 +763,10 @@
<parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -741,8 +784,10 @@
<parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
......@@ -750,8 +795,48 @@
<parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
<parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
<parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
<parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
<parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
<parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SG" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
......
boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
+ 6
− 5
View file @ a75c21af
......@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -86,7 +87,7 @@
<module
name="system_pll_inst"
kind="altera_iopll"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
......@@ -360,14 +361,14 @@
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
<parameter name="gui_reference_clock_frequency" value="25.0" />
<parameter name="gui_reference_clock_frequency" value="200.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
<parameter name="system_info_device_component" value="10AX115U4F45I3SG" />
<parameter name="system_info_device_component" value="10AX115U4F45I3SGES" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="3" />
<parameter name="system_part_trait_speed_grade" value="2" />
<parameter name="system_part_trait_speed_grade" value="3" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
......
boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
+ 8
− 5
View file @ a75c21af
......@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -237,16 +238,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="48" />
<parameter name="design_environment" value="NATIVE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
......@@ -282,7 +283,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
<parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
......@@ -412,8 +413,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
......
boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
+ 8
− 5
View file @ a75c21af
......@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -237,16 +238,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="24" />
<parameter name="design_environment" value="NATIVE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
......@@ -282,7 +283,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
<parameter name="enable_port_rx_pma_qpipullup" value="0" />
<parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
......@@ -412,8 +413,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
<parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
......
boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
+ 9
− 5
View file @ a75c21af
......@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -90,15 +91,16 @@
<module
name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="base_device" value="NIGHTFURY5ES" />
<parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="low" />
<parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="0" />
<parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
......@@ -106,6 +108,7 @@
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_hip_cal_done_port" value="0" />
<parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
......@@ -134,7 +137,7 @@
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
<parameter name="select_manual_config" value="0" />
<parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_capability_reg_enable" value="0" />
......@@ -142,6 +145,7 @@
<parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
<parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
......
boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
+ 2
− 1
View file @ a75c21af
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
......
boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
+ 2
− 1
View file @ a75c21af
......@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
......@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
version="14.1"
version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="24" />
......
boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+ 51
− 10
View file @ a75c21af
......@@ -295,6 +295,14 @@ architecture str of unb2_pinning is
);
end component transceiver_pll;
component sys_clkctrl is
port (
inclk : in std_logic := 'X'; -- inclk
outclk : out std_logic -- outclk
);
end component sys_clkctrl;
component system_pll is
port (
refclk : in std_logic := 'X'; -- clk
......@@ -306,6 +314,18 @@ architecture str of unb2_pinning is
);
end component system_pll;
component system_fpll is
port (
pll_refclk0 : in std_logic := 'X'; -- clk
pll_powerdown : in std_logic := 'X';
pll_locked : out std_logic;
pll_cal_busy : out std_logic;
outclk0 : out std_logic; -- outclk0
outclk1 : out std_logic; -- outclk1
outclk2 : out std_logic -- outclk2
);
end component system_fpll;
component unb2_pinning_qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
......@@ -381,6 +401,7 @@ architecture str of unb2_pinning is
signal sys_locked : std_logic := '0';
signal mm_clk : std_logic := '0';
signal clk_125 : std_logic := '0';
signal CLK_buffered : std_logic := '0';
-- signals for the ddr4 controllers
signal local_i_cal_success : std_logic;
......@@ -854,10 +875,18 @@ begin
reset_p <= not reset_n;
u0 : component sys_clkctrl
port map (
inclk => CLK, -- altclkctrl_input.inclk
outclk => CLK_buffered -- altclkctrl_output.outclk
);
u_system_pll : system_pll
port map(
refclk => ETH_CLK,
-- refclk => CLK,
-- refclk => ETH_CLK,
refclk => CLK_buffered,
-- refclk => INTB,
rst => reset_p,
locked => sys_locked,
outclk_0 => mm_clk, -- 100MHz
......@@ -865,6 +894,18 @@ begin
outclk_2 => clk_125 -- 125MHz for 1ge
);
-- u_system_pll : system_fpll
-- port map(
-- pll_refclk0 => INTB,
-- pll_powerdown => reset_p,
-- pll_locked => sys_locked,
-- pll_cal_busy => open,
-- outclk0 => mm_clk, -- 100MHz
-- outclk1 => sys_clk, -- 300MHz
-- outclk2 => clk_125 -- 125MHz for 1ge
-- );
-- ****** i2c interfaces ******
u_qsys : unb2_pinning_qsys
......@@ -921,10 +962,10 @@ begin
avs_i2c_master_11_i2c_scl_export => mb_scl,
eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
--eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
--eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
--eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
--eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
pio_0_external_connection_export => ver_id_pmbusalert
......@@ -935,13 +976,13 @@ begin
INTA <= inta_out when PPS = '1' else 'Z';
INTB <= intb_out when PPS = '1' else 'Z';
TESTIO <= testio_out when PPS = '1' else "ZZZZZZ";
TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
inta_in <= INTA;
intb_in <= INTB;
testio_in <= TESTIO;
testio_in(5 downto 0) <= TESTIO(5 downto 0);
qsfp_led_in <= QSFP_LED;
bck_err_in <= BCK_ERR;
......
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