From a75c21af429c6386f6ae48dd32cafad29b4b299a Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@astron.nl>
Date: Thu, 28 May 2015 12:26:42 +0000
Subject: [PATCH] pinning design compiles with Q15.0
---
.../build/quartus/unb2_pinning.qsf | 10 +-
.../build/quartus/unb2_pinning_qsys.qsys | 223 +++++++++---------
.../designs/unb2_pinning/src/ip/ddr4.qsys | 91 ++++++-
.../unb2_pinning/src/ip/system_pll.qsys | 11 +-
.../unb2_pinning/src/ip/transceiver_phy.qsys | 13 +-
.../src/ip/transceiver_phy_24channel.qsys | 13 +-
.../unb2_pinning/src/ip/transceiver_pll.qsys | 14 +-
.../src/ip/transceiver_reset_controller.qsys | 3 +-
.../ip/transceiver_reset_controller_24.qsys | 3 +-
.../unb2_pinning/src/vhdl/unb2_pinning.vhd | 61 ++++-
10 files changed, 293 insertions(+), 149 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
index a1101f9d87..2cd01b7fbd 100644
--- a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
+++ b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning.qsf
@@ -41,11 +41,10 @@ set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name TOP_LEVEL_ENTITY unb2_pinning
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:55:45 MARCH 13, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
@@ -1038,7 +1037,7 @@ set_location_assignment PIN_M16 -to MB_EVENT
#set_global_assignment -name DEVICE 10AX115U3F45I2LG
#set_global_assignment -name DEVICE 10AX115U4F45I3SGES
#set_global_assignment -name DEVICE 10AX115U4F45I2SGES
-set_global_assignment -name DEVICE 10AX115U4F45I3SG
+set_global_assignment -name DEVICE 10AX115U4F45I3SGES
@@ -1664,4 +1663,7 @@ set_global_assignment -name SIP_FILE ../../src/ip/ddr4.sip
set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_pinning.vhd
set_global_assignment -name SOURCE_FILE db/unb2_pinning.cmp.rdb
set_global_assignment -name SDC_FILE ../../src/sdc/unb2_pinning.sdc
+set_global_assignment -name QSYS_FILE ../../src/ip/system_fpll.qsys
+set_instance_assignment -name UNFORCE_MERGE_PLL ON -to "*system_pll_altera_iopll_150*|altera_pll:altera_pll_i*|*"
+set_global_assignment -name QSYS_FILE ../../src/ip/sys_clkctrl.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
index c98068836c..b12d8f5b0c 100644
--- a/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/build/quartus/unb2_pinning_qsys.qsys
@@ -492,15 +492,16 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="unb2_pinning.qpf" />
<parameter name="sopcBorderPoints" value="false" />
@@ -908,15 +909,15 @@
<parameter name="g_protocol_adr_w" value="10" />
<parameter name="g_result_adr_w" value="10" />
</module>
- <module name="clk_0" kind="clock_source" version="14.1" enabled="1">
+ <module name="clk_0" kind="clock_source" version="15.0" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
- <module name="eth_tse_0" kind="altera_eth_tse" version="14.1" enabled="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <module name="eth_tse_0" kind="altera_eth_tse" version="15.0" enabled="1">
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="deviceFamilyName" value="Arria 10" />
<parameter name="eg_addr" value="11" />
@@ -952,11 +953,12 @@
<parameter name="transceiver_type" value="LVDS_IO" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
<parameter name="use_misc_ports" value="true" />
</module>
- <module name="eth_tse_1" kind="altera_eth_tse" version="14.1" enabled="1">
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <module name="eth_tse_1" kind="altera_eth_tse" version="15.0" enabled="1">
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="core_variation" value="MAC_PCS" />
<parameter name="deviceFamilyName" value="Arria 10" />
<parameter name="eg_addr" value="11" />
@@ -992,17 +994,18 @@
<parameter name="transceiver_type" value="LVDS_IO" />
<parameter name="tstamp_fp_width" value="4" />
<parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
<parameter name="use_misc_ports" value="true" />
</module>
<module
name="nios2_qsys_0"
kind="altera_nios2_gen2"
- version="14.1"
+ version="15.0"
enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
- <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave">nios2_qsys_0.jtag_debug_module</parameter>
@@ -1040,7 +1043,7 @@
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="Arria 10" />
- <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
<parameter name="exceptionSlave" value="Absolute" />
@@ -1177,7 +1180,7 @@
<module
name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
- version="14.1"
+ version="15.0"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
@@ -1185,7 +1188,7 @@
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="initMemContent" value="true" />
@@ -1203,7 +1206,7 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
- <module name="pio_0" kind="altera_avalon_pio" version="14.1" enabled="1">
+ <module name="pio_0" kind="altera_avalon_pio" version="15.0" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
@@ -1219,7 +1222,7 @@
</module>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_0.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1228,7 +1231,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_1.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1237,7 +1240,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_2.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1246,7 +1249,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_3.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1255,7 +1258,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_4.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1264,7 +1267,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_5.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1273,7 +1276,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_6.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1282,7 +1285,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_7.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1291,7 +1294,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_8.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1300,7 +1303,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_9.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1309,7 +1312,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_10.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1318,7 +1321,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_11.control">
<parameter name="arbitrationPriority" value="1" />
@@ -1327,7 +1330,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="eth_tse_0.control_port">
<parameter name="arbitrationPriority" value="1" />
@@ -1336,7 +1339,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="eth_tse_1.control_port">
<parameter name="arbitrationPriority" value="1" />
@@ -1345,7 +1348,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="nios2_qsys_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
@@ -1354,7 +1357,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_0.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1363,7 +1366,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_1.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1372,7 +1375,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_2.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1381,7 +1384,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_3.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1390,7 +1393,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_4.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1399,7 +1402,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_5.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1408,7 +1411,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_6.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1417,7 +1420,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_7.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1426,7 +1429,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_8.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1435,7 +1438,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_9.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1444,7 +1447,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_10.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1453,7 +1456,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_11.protocol">
<parameter name="arbitrationPriority" value="1" />
@@ -1462,7 +1465,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_0.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1471,7 +1474,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_1.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1480,7 +1483,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_2.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1489,7 +1492,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_3.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1498,7 +1501,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_4.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1507,7 +1510,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_5.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1516,7 +1519,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_6.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1525,7 +1528,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_7.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1534,7 +1537,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_8.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1543,7 +1546,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_9.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1552,7 +1555,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_10.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1561,7 +1564,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="avs_i2c_master_11.result">
<parameter name="arbitrationPriority" value="1" />
@@ -1570,7 +1573,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -1579,7 +1582,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.data_master"
end="pio_0.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -1588,7 +1591,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.instruction_master"
end="nios2_qsys_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
@@ -1597,7 +1600,7 @@
</connection>
<connection
kind="avalon"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.instruction_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
@@ -1606,267 +1609,267 @@
</connection>
<connection
kind="avalon_streaming"
- version="14.1"
+ version="15.0"
start="eth_tse_0.receive"
end="eth_tse_1.transmit" />
<connection
kind="avalon_streaming"
- version="14.1"
+ version="15.0"
start="eth_tse_1.receive"
end="eth_tse_0.transmit" />
- <connection kind="clock" version="14.1" start="clk_0.clk" end="nios2_qsys_0.clk" />
- <connection kind="clock" version="14.1" start="clk_0.clk" end="pio_0.clk" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="nios2_qsys_0.clk" />
+ <connection kind="clock" version="15.0" start="clk_0.clk" end="pio_0.clk" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_0.control_port_clock_connection" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_1.control_port_clock_connection" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_0.receive_clock_connection" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_1.receive_clock_connection" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_0.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_1.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_2.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_3.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_4.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_5.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_6.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_7.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_8.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_9.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_10.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="avs_i2c_master_11.system" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_0.transmit_clock_connection" />
<connection
kind="clock"
- version="14.1"
+ version="15.0"
start="clk_0.clk"
end="eth_tse_1.transmit_clock_connection" />
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_0.interrupt">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_1.interrupt">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_2.interrupt">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_3.interrupt">
<parameter name="irqNumber" value="3" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_4.interrupt">
<parameter name="irqNumber" value="4" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_5.interrupt">
<parameter name="irqNumber" value="5" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_6.interrupt">
<parameter name="irqNumber" value="6" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_7.interrupt">
<parameter name="irqNumber" value="7" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_8.interrupt">
<parameter name="irqNumber" value="8" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_9.interrupt">
<parameter name="irqNumber" value="9" />
</connection>
<connection
kind="interrupt"
- version="14.1"
+ version="15.0"
start="nios2_qsys_0.irq"
end="avs_i2c_master_10.interrupt">
<parameter name="irqNumber" value="10" />
</connection>
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="nios2_qsys_0.reset" />
- <connection kind="reset" version="14.1" start="clk_0.clk_reset" end="pio_0.reset" />
+ <connection kind="reset" version="15.0" start="clk_0.clk_reset" end="pio_0.reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="eth_tse_0.reset_connection" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="eth_tse_1.reset_connection" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_0.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_1.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_2.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_3.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_4.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_5.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_6.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_7.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_8.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_9.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_10.system_reset" />
<connection
kind="reset"
- version="14.1"
+ version="15.0"
start="clk_0.clk_reset"
end="avs_i2c_master_11.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
index fa2b8ddf6f..c6f3663e10 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/ddr4.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="device" value="10AX115U4F45I3SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -128,7 +129,7 @@
<module
name="ddr4_inst"
kind="altera_emif"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
@@ -255,6 +256,7 @@
<parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
<parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
@@ -299,15 +301,23 @@
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC" value="3" />
+ <parameter name="CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC" value="10" />
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
<parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
@@ -316,33 +326,55 @@
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
<parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
<parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
<parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
<parameter name="DIAG_EXPORT_VJI" value="false" />
<parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
<parameter name="DIAG_EXTRA_CONFIGS" value="" />
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
<parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
<parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
<parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
<parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
@@ -645,8 +677,10 @@
<parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -665,8 +699,10 @@
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -684,8 +720,10 @@
<parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -701,10 +739,13 @@
<parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
<parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
<parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -722,8 +763,10 @@
<parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -741,8 +784,10 @@
<parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
@@ -750,8 +795,48 @@
<parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
- <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SGES" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U4F45I3SG" />
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="3" />
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_ddr4_inst</parameter>
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
index 82ccfce8d7..e3819b5f95 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/system_pll.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -86,7 +87,7 @@
<module
name="system_pll_inst"
kind="altera_iopll"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="gui_active_clk" value="false" />
@@ -360,14 +361,14 @@
<parameter name="gui_ps_units9" value="ps" />
<parameter name="gui_refclk1_frequency" value="100.0" />
<parameter name="gui_refclk_switch" value="false" />
- <parameter name="gui_reference_clock_frequency" value="25.0" />
+ <parameter name="gui_reference_clock_frequency" value="200.0" />
<parameter name="gui_switchover_delay" value="0" />
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
<parameter name="gui_use_locked" value="true" />
- <parameter name="system_info_device_component" value="10AX115U4F45I3SG" />
+ <parameter name="system_info_device_component" value="10AX115U4F45I3SGES" />
<parameter name="system_info_device_family" value="Arria 10" />
<parameter name="system_info_device_speed_grade" value="3" />
- <parameter name="system_part_trait_speed_grade" value="2" />
+ <parameter name="system_part_trait_speed_grade" value="3" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
index 5aba4471b0..5dd69701ed 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -237,16 +238,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5ES" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="48" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -282,7 +283,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -412,8 +413,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
index 3e40cb1d42..f678b33047 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_phy_24channel.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -237,16 +238,16 @@
<module
name="transceiver_phy_inst"
kind="altera_xcvr_native_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5ES" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bonded_mode" value="not_bonded" />
<parameter name="cdr_refclk_cnt" value="1" />
<parameter name="cdr_refclk_select" value="0" />
<parameter name="channels" value="24" />
<parameter name="design_environment" value="NATIVE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="duplex_mode" value="duplex" />
<parameter name="enable_hard_reset" value="0" />
@@ -282,7 +283,7 @@
<parameter name="enable_port_rx_pma_clkslip" value="0" />
<parameter name="enable_port_rx_pma_div_clkout" value="0" />
<parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
- <parameter name="enable_port_rx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
<parameter name="enable_port_rx_polinv" value="0" />
<parameter name="enable_port_rx_seriallpbken" value="0" />
<parameter name="enable_port_rx_seriallpbken_tx" value="0" />
@@ -412,8 +413,10 @@
<parameter name="set_embedded_debug_enable" value="0" />
<parameter name="set_enable_calibration" value="0" />
<parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
<parameter name="set_pcs_bonding_master" value="Auto" />
<parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
<parameter name="set_user_identifier" value="0" />
<parameter name="std_low_latency_bypass_enable" value="0" />
<parameter name="std_pcs_pma_width" value="10" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
index a2264c824a..374c81dd9e 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_pll.qsys
@@ -28,7 +28,7 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="3" />
<parameter name="fabricMode" value="QSYS" />
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -90,15 +91,16 @@
<module
name="transceiver_pll_inst"
kind="altera_xcvr_atx_pll_a10"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
- <parameter name="base_device" value="NIGHTFURY5ES" />
+ <parameter name="base_device" value="NIGHTFURY5" />
<parameter name="bw_sel" value="low" />
- <parameter name="device" value="10AX115U4F45I3SG" />
+ <parameter name="device" value="10AX115U4F45I3SGES" />
<parameter name="device_family" value="Arria 10" />
<parameter name="enable_16G_path" value="0" />
<parameter name="enable_8G_path" value="0" />
+ <parameter name="enable_atx_to_fpll_cascade_out" value="0" />
<parameter name="enable_bonding_clks" value="0" />
<parameter name="enable_cascade_out" value="0" />
<parameter name="enable_debug_ports_parameters" value="0" />
@@ -106,6 +108,7 @@
<parameter name="enable_fractional" value="0" />
<parameter name="enable_hfreq_clk" value="1" />
<parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
<parameter name="enable_mcgb" value="1" />
<parameter name="enable_mcgb_pcie_clksw" value="0" />
<parameter name="enable_pcie_clk" value="0" />
@@ -134,7 +137,7 @@
<parameter name="rcfg_txt_file_enable" value="0" />
<parameter name="refclk_cnt" value="1" />
<parameter name="refclk_index" value="0" />
- <parameter name="select_manual_config" value="0" />
+ <parameter name="select_manual_config" value="false" />
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
<parameter name="set_auto_reference_clock_frequency" value="644.53125" />
<parameter name="set_capability_reg_enable" value="0" />
@@ -142,6 +145,7 @@
<parameter name="set_fref_clock_frequency" value="100.0" />
<parameter name="set_hip_cal_en" value="0" />
<parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
<parameter name="set_l_counter" value="2" />
<parameter name="set_m_counter" value="1" />
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
index 77cf8efc4b..9b40d2b6e3 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller.qsys
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="48" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
index b42df57aa1..719550747b 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
+++ b/boards/uniboard2/designs/unb2_pinning/src/ip/transceiver_reset_controller_24.qsys
@@ -37,6 +37,7 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
@@ -146,7 +147,7 @@
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
- version="14.1"
+ version="15.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="24" />
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 7c2f5251bd..8d902c91ab 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -295,6 +295,14 @@ architecture str of unb2_pinning is
);
end component transceiver_pll;
+ component sys_clkctrl is
+ port (
+ inclk : in std_logic := 'X'; -- inclk
+ outclk : out std_logic -- outclk
+ );
+ end component sys_clkctrl;
+
+
component system_pll is
port (
refclk : in std_logic := 'X'; -- clk
@@ -306,6 +314,18 @@ architecture str of unb2_pinning is
);
end component system_pll;
+ component system_fpll is
+ port (
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_powerdown : in std_logic := 'X';
+ pll_locked : out std_logic;
+ pll_cal_busy : out std_logic;
+ outclk0 : out std_logic; -- outclk0
+ outclk1 : out std_logic; -- outclk1
+ outclk2 : out std_logic -- outclk2
+ );
+ end component system_fpll;
+
component unb2_pinning_qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
@@ -381,6 +401,7 @@ architecture str of unb2_pinning is
signal sys_locked : std_logic := '0';
signal mm_clk : std_logic := '0';
signal clk_125 : std_logic := '0';
+ signal CLK_buffered : std_logic := '0';
-- signals for the ddr4 controllers
signal local_i_cal_success : std_logic;
@@ -853,18 +874,38 @@ begin
);
reset_p <= not reset_n;
-
+
+ u0 : component sys_clkctrl
+ port map (
+ inclk => CLK, -- altclkctrl_input.inclk
+ outclk => CLK_buffered -- altclkctrl_output.outclk
+ );
+
+
u_system_pll : system_pll
port map(
- refclk => ETH_CLK,
--- refclk => CLK,
+-- refclk => ETH_CLK,
+ refclk => CLK_buffered,
+-- refclk => INTB,
rst => reset_p,
locked => sys_locked,
outclk_0 => mm_clk, -- 100MHz
outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
+ outclk_2 => clk_125 -- 125MHz for 1ge
);
+-- u_system_pll : system_fpll
+-- port map(
+-- pll_refclk0 => INTB,
+-- pll_powerdown => reset_p,
+-- pll_locked => sys_locked,
+-- pll_cal_busy => open,
+-- outclk0 => mm_clk, -- 100MHz
+-- outclk1 => sys_clk, -- 300MHz
+-- outclk2 => clk_125 -- 125MHz for 1ge
+-- );
+
+
-- ****** i2c interfaces ******
u_qsys : unb2_pinning_qsys
@@ -921,10 +962,10 @@ begin
avs_i2c_master_11_i2c_scl_export => mb_scl,
eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
- eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
- --eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
- --eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
pio_0_external_connection_export => ver_id_pmbusalert
@@ -935,13 +976,13 @@ begin
INTA <= inta_out when PPS = '1' else 'Z';
INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO <= testio_out when PPS = '1' else "ZZZZZZ";
+ TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
inta_in <= INTA;
intb_in <= INTB;
- testio_in <= TESTIO;
+ testio_in(5 downto 0) <= TESTIO(5 downto 0);
qsfp_led_in <= QSFP_LED;
bck_err_in <= BCK_ERR;
--
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