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Commit a6b90cce authored by Eric Kooistra's avatar Eric Kooistra
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Use tech_eth_10g.

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libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+ 116
− 127
View file @ a6b90cce
......@@ -30,7 +30,7 @@
--
--
LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_mac_10g_lib;
LIBRARY IEEE, common_lib, dp_lib, diag_lib, technology_lib, tech_mac_10g_lib, tech_eth_10g_lib, tr_xaui_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -54,12 +54,14 @@ ENTITY tr_10GbE IS
g_word_alignment_padding : BOOLEAN := FALSE
);
PORT (
tr_clk_644 : IN STD_LOGIC := '0';
tr_clk_312 : IN STD_LOGIC := '0';
tr_clk_156 : IN STD_LOGIC := '0';
tr_rst_156 : IN STD_LOGIC := '0';
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
tr_ref_clk_312 : IN STD_LOGIC := '0'; -- 312.5 MHz for 10GBASE-R
tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.25 MHz for 10GBASE-R or for XAUI
tr_ref_rst_156 : IN STD_LOGIC := '0'; -- for 10GBASE-R or for XAUI
cal_rec_clk : IN STD_LOGIC;
-- Calibration & reconfig clock
cal_rec_clk : IN STD_LOGIC := '0'; -- for XAUI;
-- MM interface
mm_rst : IN STD_LOGIC;
......@@ -85,12 +87,12 @@ ENTITY tr_10GbE IS
src_out_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
-- Serial XAUI IO
xaui_tx_out_arr : OUT t_xaui_arr(g_nof_macs-1 DOWNTO 0);
xaui_rx_in_arr : IN t_xaui_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
xaui_tx_arr : OUT t_xaui_arr(g_nof_macs-1 DOWNTO 0);
xaui_rx_arr : IN t_xaui_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
-- Serial IO
serial_tx_out_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0);
serial_rx_in_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0');
serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0);
serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0');
-- MDIO interface
mdio_rst : OUT STD_LOGIC;
......@@ -103,20 +105,21 @@ END tr_10GbE;
ARCHITECTURE str OF tr_10GbE IS
CONSTANT c_mac_mm_addr_w : NATURAL := 13;
CONSTANT c_fifo_margin : NATURAL := g_pkt_len;
SIGNAL tr_clk : STD_LOGIC;
SIGNAL tr_rst : STD_LOGIC;
SIGNAL tx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL tx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL tx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL rx_clk_arr_out : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL rx_rst_arr_out : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL rx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL rx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_ref_clk_644 : STD_LOGIC;
SIGNAL eth_ref_clk_312 : STD_LOGIC;
SIGNAL eth_ref_clk_156 : STD_LOGIC;
SIGNAL eth_ref_rst_156 : STD_LOGIC;
SIGNAL reg_mac_mosi_arr : t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL reg_mac_miso_arr : t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_tx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_rx_clk_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL eth_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_dc_tx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_dc_tx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
......@@ -130,20 +133,45 @@ ARCHITECTURE str OF tr_10GbE IS
SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
SIGNAL mac_xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_macs-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------------------------------
-- Clocks and reset
---------------------------------------------------------------------------------------
-- tx_clk_arr = tr_clk_156 = tr_clk
tr_clk <= tr_clk_156;
tr_rst <= tr_rst_156;
tx_clk_arr <= (OTHERS=>tr_clk_156);
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : ENTITY tech_eth_10g_lib.tech_eth_10g_clocks
GENERIC MAP (
g_technology => g_technology,
g_nof_channels => 1
)
PORT MAP (
-- Input clocks
-- . Reference
tr_ref_clk_644 => tr_ref_clk_644,
tr_ref_clk_312 => tr_ref_clk_312,
tr_ref_clk_156 => tr_ref_clk_156,
tr_ref_rst_156 => tr_ref_rst_156,
-- . XAUI
tx_rst_arr => tx_rst_arr_out,
rx_clk_arr => rx_clk_arr_out,
rx_rst_arr => rx_rst_arr_out,
-- Output clocks
-- . Reference
eth_ref_clk_644 => eth_ref_clk_644,
eth_ref_clk_312 => eth_ref_clk_312,
eth_ref_clk_156 => eth_ref_clk_156,
eth_ref_rst_156 => eth_ref_rst_156,
-- . Data
eth_tx_clk_arr => eth_tx_clk_arr,
eth_tx_rst_arr => eth_tx_rst_arr,
eth_rx_clk_arr => eth_rx_clk_arr,
eth_rx_rst_arr => eth_rx_rst_arr
);
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> tx_clk
......@@ -158,8 +186,8 @@ BEGIN
PORT MAP (
wr_rst => dp_rst,
wr_clk => dp_clk,
rd_rst => tx_rst_arr(i),
rd_clk => tx_clk_arr(i),
rd_rst => eth_tx_rst_arr(i),
rd_clk => eth_tx_clk_arr(i),
snk_out => snk_out_arr(i),
snk_in => snk_in_arr(i),
......@@ -182,8 +210,8 @@ BEGIN
g_fifo_size => g_pkt_len+c_fifo_margin
)
PORT MAP (
rst => tx_rst_arr(i),
clk => tx_clk_arr(i),
rst => eth_tx_rst_arr(i),
clk => eth_tx_clk_arr(i),
snk_out => dp_fifo_dc_tx_src_in_arr(i),
snk_in => dp_fifo_dc_tx_src_out_arr(i),
......@@ -195,84 +223,60 @@ BEGIN
---------------------------------------------------------------------------------------
-- DP-MAC connect
-- ETH MAC + PHY
---------------------------------------------------------------------------------------
gen_tech_mac_10g : FOR i IN 0 TO g_nof_macs-1 GENERATE
u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
GENERIC MAP (
g_technology => g_technology,
g_pre_header_padding => g_word_alignment_padding
)
PORT MAP (
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
csr_mosi => reg_mac_mosi_arr(i), -- CSR = control status register
csr_miso => reg_mac_miso_arr(i),
-- ST
tx_clk_156 => tx_clk_arr(i), -- 156.25 MHz local reference
tx_rst => tx_rst_arr(i),
tx_snk_in => dp_fifo_fill_tx_src_out_arr(i), -- 64 bit data
tx_snk_out => dp_fifo_fill_tx_src_in_arr(i),
rx_clk_156 => rx_clk_arr(i), -- 156.25 MHz
rx_rst => rx_rst_arr(i),
rx_src_out => mac_10g_src_out_arr(i), -- 64 bit data
rx_src_in => mac_10g_src_in_arr(i),
-- XGMII
xgmii_tx_data => mac_xgmii_tx_dc_arr(i), -- 72 bit
xgmii_rx_data => mac_xgmii_rx_dc_arr(i) -- 72 bit
);
END GENERATE;
---------------------------------------------------------------------------------------
-- XGMII-XAUI connect
---------------------------------------------------------------------------------------
u_tr_xaui : ENTITY tr_xaui_lib.tr_xaui
u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
GENERIC MAP (
g_technology => g_technology,
g_sim => g_sim,
g_sim_level => g_sim_level,
g_use_xgmii => TRUE, -- Use XGMII direct
g_nof_xaui => g_nof_macs,
g_use_mdio => g_use_mdio,
g_mdio_epcs_dis => g_mdio_epcs_dis
g_sim_level => g_sim_level, -- 0 = use IP; 1 = use fast serdes model
g_nof_channels => g_nof_macs,
g_link_status_check => "11",
g_pre_header_padding => g_word_alignment_padding
)
PORT MAP (
-- Transceiver PLL reference clock
tr_clk => tr_clk, -- = tr_clk_156 = tx_clk_arr
tr_rst => tr_rst, -- = tr_rst_156
tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
-- Calibration & reconfig clock
cal_rec_clk => cal_rec_clk,
cal_rec_clk => cal_rec_clk, -- for XAUI;
-- MM clock for register of optional MDIO master
-- XAUI clocks
tx_clk_arr_in => eth_tx_clk_arr, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
tx_rst_arr_out => tx_rst_arr_out,
rx_clk_arr_out => rx_clk_arr_out,
rx_clk_arr_in => eth_rx_clk_arr, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
rx_rst_arr_out => rx_rst_arr_out,
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
-- Streaming TX interfaces
tx_clk_arr => tx_clk_arr,
tx_rst_arr => tx_rst_arr,
mac_mosi => reg_mac_mosi, -- MAG_10G (CSR), aggregated for all g_nof_channels
mac_miso => reg_mac_miso,
xaui_mosi => xaui_mosi, -- XAUI control
xaui_miso => xaui_miso,
-- Streaming RX interfaces
rx_clk_arr_out => rx_clk_arr,
rx_clk_arr_in => rx_clk_arr,
rx_rst_arr => rx_rst_arr,
-- ST
tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr ,
-- Direct XGMII interface
xgmii_tx_dc_arr => mac_xgmii_tx_dc_arr,
xgmii_rx_dc_arr => mac_xgmii_rx_dc_arr,
rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
rx_src_in_arr => mac_10g_src_in_arr,
--Serial I/O
xaui_tx_arr => xaui_tx_out_arr,
xaui_rx_arr => xaui_rx_in_arr,
-- PHY serial IO
-- . 10GBASE-R (single lane)
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr,
-- XAUI PHY IP MM control/status
xaui_mosi => xaui_mosi,
xaui_miso => xaui_miso
-- . XAUI (four lanes)
xaui_tx_arr => xaui_tx_arr,
xaui_rx_arr => xaui_rx_arr
);
---------------------------------------------------------------------------
......@@ -287,8 +291,8 @@ BEGIN
)
PORT MAP (
-- Transceiver PLL reference clock
tr_clk => tr_clk,
tr_rst => tr_rst,
tr_clk => eth_ref_clk_156,
tr_rst => eth_ref_rst_156,
-- MM clock for register of optional MDIO master
mm_clk => mm_clk,
......@@ -317,8 +321,8 @@ BEGIN
g_use_empty => TRUE
)
PORT MAP (
wr_rst => rx_rst_arr(i),
wr_clk => rx_clk_arr(i),
wr_rst => eth_rx_rst_arr(i),
wr_clk => eth_rx_clk_arr(i),
rd_rst => dp_rst,
rd_clk => dp_clk,
......@@ -347,19 +351,4 @@ BEGIN
);
END GENERATE;
-----------------------------------------------------------------------------
-- MM bus muxes
-----------------------------------------------------------------------------
u_common_mem_mux : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_macs,
g_mult_addr_w => c_mac_mm_addr_w
)
PORT MAP (
mosi => reg_mac_mosi,
miso => reg_mac_miso,
mosi_arr => reg_mac_mosi_arr,
miso_arr => reg_mac_miso_arr
);
END str;
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