Skip to content
Snippets Groups Projects
Commit 11f6dd6e authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Connect dp_clk directly. Connect tr_ref_clk_*, but only support XAUI yet.

parent d868d1ae
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+ 38
− 45
View file @ 11f6dd6e
......@@ -72,7 +72,7 @@ ARCHITECTURE tb OF tb_tr_10GbE IS
CONSTANT dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT cal_clk_period : TIME := 25 ns; -- 40 MHz
CONSTANT clk_156_period : TIME := 6.4 ns; -- 156.25 MHz
CONSTANT phy_delay : TIME := sel_a_b(g_sim_level>0, clk_156_period*1, 1 ns); -- the sim_xaui only works without unit PHY delays
CONSTANT phy_delay : TIME := sel_a_b(g_sim_level>0, 0 ns, 1 ns); -- the sim_xaui and sim_10gbase_r only work with zero or tr_clk delays
CONSTANT c_nof_channels : NATURAL := 1;
CONSTANT c_rl : NATURAL := 1;
......@@ -97,18 +97,15 @@ ARCHITECTURE tb OF tb_tr_10GbE IS
-- Clocks and reset
SIGNAL rx_end : STD_LOGIC := '0';
SIGNAL clk_644 : STD_LOGIC := '1'; -- 644.53125 MHz
SIGNAL clk_312 : STD_LOGIC := '1'; -- 312.5 MHz
SIGNAL clk_156 : STD_LOGIC := '1'; -- 156.25 MHz
SIGNAL rst_156 : STD_LOGIC; -- reset synchronous with clk_156
SIGNAL cal_clk : STD_LOGIC := '1'; -- calibration clock
SIGNAL mm_clk : STD_LOGIC := '1'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
SIGNAL dp_clk : STD_LOGIC := '1'; -- data path clock
SIGNAL dp_rst : STD_LOGIC; -- reset synchronous with dp_clk
SIGNAL clk_644 : STD_LOGIC := '1'; -- 644.53125 MHz
SIGNAL clk_156 : STD_LOGIC := '1'; -- 156.25 MHz
SIGNAL rst_156 : STD_LOGIC; -- reset synchronous with clk_156
SIGNAL tx_clk : STD_LOGIC;
SIGNAL tx_rst : STD_LOGIC; -- reset synchronous with tx_clk
SIGNAL rx_clk : STD_LOGIC;
SIGNAL rx_rst : STD_LOGIC; -- reset synchronous with rx_clk
-- MAC 10G control interface
SIGNAL mm_init : STD_LOGIC := '1';
......@@ -135,12 +132,12 @@ ARCHITECTURE tb OF tb_tr_10GbE IS
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
-- PHY XAUI serial I/O
SIGNAL xaui_tx_out_arr : t_xaui_arr(c_nof_channels-1 DOWNTO 0);
SIGNAL xaui_rx_in_arr : t_xaui_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_channels-1 DOWNTO 0);
SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
-- PHY 10GBASE-R serial IO
SIGNAL serial_tx_out_arr : STD_LOGIC_VECTOR(c_nof_channels-1 downto 0);
SIGNAL serial_rx_in_arr : STD_LOGIC_VECTOR(c_nof_channels-1 downto 0) := (OTHERS=>'0');
SIGNAL serial_tx_arr : STD_LOGIC_VECTOR(c_nof_channels-1 downto 0);
SIGNAL serial_rx_arr : STD_LOGIC_VECTOR(c_nof_channels-1 downto 0) := (OTHERS=>'0');
-- Verification
SIGNAL expected_sosi_arr : t_dp_sosi_arr(0 TO c_nof_pkt-1);
......@@ -160,8 +157,6 @@ BEGIN
mm_rst <= '1', '0' AFTER mm_clk_period*10;
dp_rst <= '1', '0' AFTER dp_clk_period*10;
rst_156 <= '1', '0' AFTER clk_156_period*4;
tx_rst <= '1', '0' AFTER clk_156_period*10;
rx_rst <= '1', '0' AFTER clk_156_period*10;
-- debug signals to ease monitoring in wave window
tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
......@@ -198,9 +193,9 @@ BEGIN
tx_sosi <= c_dp_sosi_rst;
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(tx_clk);
WAIT UNTIL rising_edge(dp_clk);
END LOOP;
proc_common_wait_some_cycles(tx_clk, 10);
proc_common_wait_some_cycles(dp_clk, 10);
-- Loopback txp->rxp so use promiscuous mode or use DST_MAC = c_src_mac to send to itself
......@@ -210,12 +205,12 @@ BEGIN
-- . For I>46 the payload length is I and empty = 4 - (I mod 4)
FOR I IN 0 TO c_nof_pkt-1 LOOP
proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_clk, tx_en, tx_siso, tx_sosi);
proc_common_wait_some_cycles(tx_clk, 0);
proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, dp_clk, tx_en, tx_siso, tx_sosi);
proc_common_wait_some_cycles(dp_clk, 0);
END LOOP;
proc_common_wait_some_cycles(tx_clk, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
proc_common_wait_some_cycles(tx_clk, 100);
proc_common_wait_some_cycles(dp_clk, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
proc_common_wait_some_cycles(dp_clk, 100);
rx_end <= '1';
WAIT;
END PROCESS;
......@@ -227,12 +222,12 @@ BEGIN
rx_siso <= c_dp_siso_hold;
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(rx_clk);
WAIT UNTIL rising_edge(dp_clk);
END LOOP;
-- Receive forever
WHILE TRUE LOOP
proc_tech_mac_10g_rx_packet(total_header, g_data_type, rx_clk, rx_sosi, rx_siso);
proc_tech_mac_10g_rx_packet(total_header, g_data_type, dp_clk, rx_sosi, rx_siso);
rx_toggle <= NOT rx_toggle;
END LOOP;
......@@ -240,10 +235,10 @@ BEGIN
END PROCESS;
p_ff_store_tx_sosi_at_eop : PROCESS(tx_clk)
p_ff_store_tx_sosi_at_eop : PROCESS(dp_clk)
VARIABLE vI : NATURAL := 0;
BEGIN
IF rising_edge(tx_clk) THEN
IF rising_edge(dp_clk) THEN
IF tx_sosi.eop='1' THEN
expected_sosi_arr(vI) <= tx_sosi;
vI := vI +1;
......@@ -251,11 +246,11 @@ BEGIN
END IF;
END PROCESS;
p_ff_verify_rx_sosi_at_eop : PROCESS(rx_clk)
p_ff_verify_rx_sosi_at_eop : PROCESS(dp_clk)
VARIABLE vI : NATURAL := 0;
VARIABLE vLow : NATURAL := 0;
BEGIN
IF rising_edge(rx_clk) THEN
IF rising_edge(dp_clk) THEN
rx_sosi_reg <= rx_sosi; -- use rx_sosi_reg for verification at eop to account for once cycle latency in expected_sosi_arr()
IF rx_sosi_reg.eop='1' THEN
IF g_no_dut=FALSE THEN
......@@ -279,17 +274,11 @@ BEGIN
END PROCESS;
no_dut : IF g_no_dut=TRUE GENERATE
tx_clk <= clk_156;
rx_clk <= clk_156;
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
END GENERATE;
gen_dut : IF g_no_dut=FALSE GENERATE
tx_clk <= dp_clk;
rx_clk <= dp_clk;
tx_siso <= tx_siso_arr(0);
tx_sosi_arr(0) <= tx_sosi;
......@@ -308,9 +297,13 @@ BEGIN
g_word_alignment_padding => TRUE
)
PORT MAP (
tr_clk_156 => clk_156,
tr_rst_156 => rst_156,
-- Transceiver PLL reference clock
tr_ref_clk_644 => clk_644, -- 644.531250 MHz for 10GBASE-R
tr_ref_clk_312 => clk_312, -- 312.5 MHz for 10GBASE-R
tr_ref_clk_156 => clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
tr_ref_rst_156 => rst_156, -- for 10GBASE-R or for XAUI
-- Calibration & reconfig clock
cal_rec_clk => cal_clk,
-- MM interface
......@@ -327,8 +320,8 @@ BEGIN
mdio_miso_arr => OPEN,
-- DP interface
dp_rst => tx_rst,
dp_clk => tx_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
snk_out_arr => tx_siso_arr,
snk_in_arr => tx_sosi_arr,
......@@ -337,12 +330,12 @@ BEGIN
src_out_arr => rx_sosi_arr,
-- Serial XAUI interface
xaui_tx_out_arr => xaui_tx_out_arr,
xaui_rx_in_arr => xaui_rx_in_arr,
xaui_tx_arr => xaui_tx_arr,
xaui_rx_arr => xaui_rx_arr,
-- Serial IO
serial_tx_out_arr => serial_tx_out_arr,
serial_rx_in_arr => serial_rx_in_arr,
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr,
-- MDIO interface
mdio_rst => OPEN,
......@@ -353,12 +346,12 @@ BEGIN
END GENERATE;
-- Loopback PHY
xaui_rx_in_arr <= TRANSPORT xaui_tx_out_arr AFTER phy_delay; -- XAUI
serial_rx_in_arr <= TRANSPORT serial_tx_out_arr AFTER phy_delay; -- 10GBASE-R
xaui_rx_arr <= TRANSPORT xaui_tx_arr AFTER phy_delay; -- XAUI
serial_rx_arr <= TRANSPORT serial_tx_arr AFTER phy_delay; -- 10GBASE-R
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(tx_clk);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(rx_clk);
tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(dp_clk);
rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(dp_clk);
p_tb_end : PROCESS
BEGIN
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment