Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated...

Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. The parameters that are different are added and commented out. For <fifo_name>=dc_mixed_widths: In the range specification of std_logic_vectors within component ports, used_port'range is employed. However, for quicker referencing, it is preferable to specify the range in the same manner as with entity ports.

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_fifo_1921_kss5lzq.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_dc;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc is
+    component  dcfifo
+    generic (
+        -- enable_ecc  : string;
+        intended_device_family  : string;
+        -- lpm_hint  : string;
+        lpm_numwords  : natural;
+        lpm_showahead  : string;
+        lpm_type  : string;
+        lpm_width  : natural;
+        lpm_widthu  : natural;
+        overflow_checking  : string;
+        rdsync_delaypipe  : natural;
+        read_aclr_synch  : string;
+        underflow_checking  : string;
+        use_eab  : string;
+        write_aclr_synch  : string;
+        wrsync_delaypipe  : natural
+    );
+    port (
+        aclr   : in std_logic;
+        data   : in std_logic_vector(g_dat_w - 1 downto 0);
+        rdclk   : in std_logic;
+        rdreq   : in std_logic;
+        wrclk   : in std_logic;
+        wrreq   : in std_logic;
+        q   : out std_logic_vector(g_dat_w - 1 downto 0);
+        rdempty   : out std_logic;
+        rdusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0);
+        wrfull   : out std_logic;
+        wrusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+    );
+    end component;
+begin
+  u_dcfifo : dcfifo
+  generic map (
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    -- lpm_hint  => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "dcfifo",
+    lpm_width  => g_dat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    overflow_checking  => "ON",
+    rdsync_delaypipe  => 5,
+    read_aclr_synch  => "OFF",
+    underflow_checking  => "ON",
+    use_eab  => g_use_eab,
+    write_aclr_synch  => "ON",
+    wrsync_delaypipe  => 5
+  )
+  port map (
+    aclr => aclr,
+    data => data,
+    rdclk => rdclk,
+    rdreq => rdreq,
+    wrclk => wrclk,
+    wrreq => wrreq,
+    q => q,
+    rdempty => rdempty,
+    rdusedw => rdusedw,
+    wrfull => wrfull,
+    wrusedw => wrusedw
+  );
+end SYN;

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_dc_mixed_widths.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
+-- Remark:
+--   Default value for g_nof_words is 1024 and for g_wrdat_w is 20, exactly fills one M20k block ram. 20 * 1024 = 20480 block memory bits.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_dc_mixed_widths is
+  generic (
+    g_nof_words : natural := 1024;  -- FIFO size in nof wr_dat words;
+    g_wrdat_w   : natural := 20;
+    g_rddat_w   : natural := 10     
+  );
+  port (
+    aclr    : in std_logic  := '0';
+    data    : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q       : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty : out std_logic;
+    rdusedw : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull  : out std_logic;
+    wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_dc_mixed_widths;
+
+architecture SYN of ip_agi027_xxxx_fifo_dc_mixed_widths is
+  component  dcfifo_mixed_widths
+  generic (
+    -- enable_ecc  : string;
+    intended_device_family  : string;
+    -- lpm_hint  : string;
+    lpm_numwords  : natural;
+    lpm_showahead  : string;
+    lpm_type  : string;
+    lpm_width  : natural;
+    lpm_widthu  : natural;
+    lpm_widthu_r  : natural;
+    lpm_width_r  : natural;
+    overflow_checking  : string;
+    rdsync_delaypipe  : natural;
+    read_aclr_synch  : string;
+    underflow_checking  : string;
+    use_eab  : string;
+    write_aclr_synch  : string;
+    wrsync_delaypipe  : natural
+  );
+  port (
+    aclr   : in std_logic;
+    data   : in std_logic_vector(g_wrdat_w - 1 downto 0);
+    rdclk   : in std_logic;
+    rdreq   : in std_logic;
+    wrclk   : in std_logic;
+    wrreq   : in std_logic;
+    q   : out std_logic_vector(g_rddat_w - 1 downto 0);
+    rdempty   : out std_logic;
+    rdusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w) - 1 downto 0);
+    wrfull   : out std_logic;
+    wrusedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+begin
+  dcfifo_mixed_widths_component : dcfifo_mixed_widths
+  generic map (
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    -- lpm_hint  => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "dcfifo_mixed_widths",
+    lpm_width  => g_wrdat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    lpm_widthu_r  => tech_ceil_log2(g_nof_words * g_wrdat_w / g_rddat_w),
+    lpm_width_r  => g_rddat_w,
+    overflow_checking  => "ON",
+    rdsync_delaypipe  => 5,
+    read_aclr_synch  => "OFF",
+    underflow_checking  => "ON",
+    use_eab  => "ON",
+    write_aclr_synch  => "ON",
+    wrsync_delaypipe  => 5
+  )
+  port map (
+    aclr => aclr,
+    data => data,
+    rdclk => rdclk,
+    rdreq => rdreq,
+    wrclk => wrclk,
+    wrreq => wrreq,
+    q => q,
+    rdempty => rdempty,
+    rdusedw => rdusedw,
+    wrfull => wrfull,
+    wrusedw => wrusedw
+  );
+end SYN;

libraries/technology/ip_agi027_xxxx/fifo/ip_agi027_xxxx_fifo_sc.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: D.F. Brouwer
+-- Purpose: 
+--   RadioHDL wrapper / Instantiate FIFO IP with generics
+-- Description:
+--   Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_xxxx_fifo_sc_fifo_1921_7egef6q.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library technology_lib;
+use technology_lib.technology_pkg.all;
+
+library altera_mf;
+use altera_mf.all;
+
+entity ip_agi027_xxxx_fifo_sc is
+  generic (
+    g_use_eab   : string := "ON";
+    g_dat_w     : natural := 20;
+    g_nof_words : natural := 1024
+  );
+  port (
+    aclr    : in std_logic;
+    clock   : in std_logic;
+    data    : in std_logic_vector(g_dat_w - 1 downto 0);
+    rdreq   : in std_logic;
+    wrreq   : in std_logic;
+    empty   : out std_logic;
+    full    : out std_logic;
+    q       : out std_logic_vector(g_dat_w - 1 downto 0);
+    usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+end ip_agi027_xxxx_fifo_sc;
+
+architecture SYN of ip_agi027_xxxx_fifo_sc is
+  component  scfifo
+  generic (
+      add_ram_output_register  : string;
+      -- enable_ecc  : string;
+      intended_device_family  : string;
+      lpm_numwords  : natural;
+      lpm_showahead  : string;
+      lpm_type  : string;
+      lpm_width  : natural;
+      lpm_widthu  : natural;
+      overflow_checking  : string;
+      underflow_checking  : string;
+      use_eab  : string
+  );
+  port (
+      aclr   : in std_logic;
+      clock   : in std_logic;
+      data   : in std_logic_vector(g_dat_w - 1 downto 0);
+      rdreq   : in std_logic;
+      wrreq   : in std_logic;
+      empty   : out std_logic;
+      full   : out std_logic;
+      q   : out std_logic_vector(g_dat_w - 1 downto 0);
+      usedw   : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
+  );
+  end component;
+begin
+  u_scfifo : scfifo
+  generic map (
+    add_ram_output_register  => "ON",
+    -- enable_ecc  => "FALSE",
+    intended_device_family  => "Agilex 7",
+    lpm_numwords  => g_nof_words,
+    lpm_showahead  => "OFF",
+    lpm_type  => "scfifo",
+    lpm_width  => g_dat_w,
+    lpm_widthu  => tech_ceil_log2(g_nof_words),
+    overflow_checking  => "ON",
+    underflow_checking  => "ON",
+    use_eab  => g_use_eab
+  )
+  port map (
+    aclr => aclr,
+    clock => clock,
+    data => data,
+    rdreq => rdreq,
+    wrreq => wrreq,
+    empty => empty,
+    full => full,
+    q => q,
+    usedw => usedw
+  );
+end SYN;