-Passed on existing g_true_dual_port from common_ram_crw_crw upwards through

 wrapper entities;
-Set g_true_dual_port to FALSE in common_shiftram to save resources;
-Added generic to common_shiftram to indicate a fixed shift value to 
 improve timing.

libraries/base/common/src/vhdl/common_ram_r_w.vhd

@@ -28,7 +28,8 @@ ENTITY common_ram_r_w IS
   GENERIC (
     g_technology : NATURAL := c_tech_select_default;
     g_ram        : t_c_mem := c_mem_ram;
-    g_init_file  : STRING := "UNUSED"
+    g_init_file  : STRING := "UNUSED";
+    g_true_dual_port : BOOLEAN := TRUE
   );
   PORT (
     rst       : IN  STD_LOGIC := '0';
@@ -56,7 +57,8 @@ BEGIN
   GENERIC MAP (
     g_technology => g_technology,
     g_ram        => g_ram,
-    g_init_file  => g_init_file
+    g_init_file  => g_init_file,
+    g_true_dual_port => g_true_dual_port
   )
   PORT MAP (
     rst       => rst,

libraries/base/common/src/vhdl/common_ram_rw_rw.vhd

@@ -28,7 +28,8 @@ ENTITY common_ram_rw_rw IS
   GENERIC (
     g_technology : NATURAL := c_tech_select_default;
     g_ram        : t_c_mem := c_mem_ram;
-    g_init_file  : STRING := "UNUSED"
+    g_init_file  : STRING := "UNUSED";
+    g_true_dual_port : BOOLEAN := TRUE
   );
   PORT (
     rst       : IN  STD_LOGIC := '0';
@@ -60,7 +61,8 @@ BEGIN
   GENERIC MAP (
     g_technology => g_technology,
     g_ram        => g_ram,
-    g_init_file  => g_init_file
+    g_init_file  => g_init_file,
+    g_true_dual_port => g_true_dual_port
   )
   PORT MAP (
     rst_a     => rst,

libraries/technology/ip_stratixiv/ram/ip_stratixiv_ram_crw_crw.vhd

@@ -4,7 +4,7 @@
 -- MODULE: altsyncram 
 
 -- ============================================================
--- File Name: ip_stratixiv_ram_crw_crw.vhd
+-- File Name: ram_crw_crw.vhd
 -- Megafunction Name(s):
 -- 			altsyncram
 --
@@ -33,15 +33,14 @@
 --applicable agreement for further details.
 
 
-LIBRARY ieee;
+LIBRARY ieee, common_lib;
 USE ieee.std_logic_1164.all;
+USE common_lib.common_pkg.ALL;
+
 
 LIBRARY altera_mf;
 USE altera_mf.all;
 
-LIBRARY technology_lib;
-USE technology_lib.technology_pkg.ALL;
-
 ENTITY ip_stratixiv_ram_crw_crw IS
   GENERIC (
     g_adr_w      : NATURAL := 5;
@@ -72,8 +71,8 @@ END ip_stratixiv_ram_crw_crw;
 
 ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
 
-  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
-  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+  CONSTANT c_outdata_reg_a : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+  CONSTANT c_outdata_reg_b : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
@@ -299,11 +298,11 @@ END SYN;
 -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
 -- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
 -- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_crw_crw_wave*.jpg FALSE
 -- Retrieval info: LIB_FILE: altera_mf