Rename mm_mosi by mac_mosi.

libraries/technology/mac_10g/tb_tech_mac_10g.vhd

@@ -61,8 +61,6 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
   CONSTANT clk_156_period       : TIME :=  6.4 ns;  -- 156.25 MHz
   CONSTANT phy_delay            : TIME :=  0 ns;
   
-  CONSTANT c_rl                 : NATURAL := 1;
-  CONSTANT c_nof_tx_not_valid   : NATURAL := 0;  -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
   CONSTANT c_pkt_length_arr     : t_nat_natural_arr := array_init(0, 50, 1) & (1472, 1473) & 9000;  -- frame longer than 1518-46 = 1472 is received with rx_sosi.err = 8
                                                                                                     -- jumbo frame is 9018-46 = 8972
   CONSTANT c_nof_pkt            : NATURAL := c_pkt_length_arr'LENGTH;
@@ -96,11 +94,11 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
 
   -- 10G MAC control interface
   SIGNAL mm_init           : STD_LOGIC := '1';
-  SIGNAL mm_mosi           : t_mem_mosi;
-  SIGNAL mm_mosi_wrdata    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- 32 bit;
-  SIGNAL mm_miso           : t_mem_miso;
-  SIGNAL mm_miso_rdval     : STD_LOGIC;
-  SIGNAL mm_miso_rddata    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- 32 bit;
+  SIGNAL mac_mosi          : t_mem_mosi;
+  SIGNAL mac_mosi_wrdata   : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- 32 bit;
+  SIGNAL mac_miso          : t_mem_miso;
+  SIGNAL mac_miso_rdval    : STD_LOGIC;
+  SIGNAL mac_miso_rddata   : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- 32 bit;
   
   -- 10G MAC transmit interface
   -- . The tb is the ST source
@@ -137,9 +135,9 @@ BEGIN
   rx_rst <= '1', '0' AFTER clk_156_period*10;
 
   -- debug signals to ease monitoring in wave window  
-  mm_mosi_wrdata <= mm_mosi.wrdata(c_word_w-1 DOWNTO 0);
-  mm_miso_rddata <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
-  mm_miso_rdval <= '1' WHEN mm_mosi.rd='1' AND mm_miso.waitrequest='0' ELSE '0';  -- c_rd_latency = 1
+  mac_mosi_wrdata <= mac_mosi.wrdata(c_word_w-1 DOWNTO 0);
+  mac_miso_rddata <= mac_miso.rddata(c_word_w-1 DOWNTO 0);
+  mac_miso_rdval <= '1' WHEN mac_mosi.rd='1' AND mac_miso.waitrequest='0' ELSE '0';  -- c_rd_latency = 1
   
   tx_sosi_data <= tx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
   rx_sosi_data <= rx_sosi.data(c_tech_mac_10g_data_w-1 DOWNTO 0);
@@ -157,8 +155,8 @@ BEGIN
     mm_clk    => mm_clk,
     mm_rst    => mm_rst,
     mm_init   => mm_init,
-    mm_mosi   => mm_mosi,
-    mm_miso   => mm_miso
+    mac_mosi  => mac_mosi,
+    mac_miso  => mac_miso
   );
 
   -- Packet transmitter
@@ -170,7 +168,7 @@ BEGIN
   PORT MAP (
     mm_init        => mm_init,
     total_header   => total_header,
-    clk_156        => tx_ref_clk_156,
+    tx_clk         => tx_ref_clk_156,
     tx_siso        => tx_siso,
     tx_sosi        => tx_sosi,
     link_fault     => OPEN,
@@ -193,8 +191,8 @@ BEGIN
       -- MM
       mm_clk            => mm_clk,
       mm_rst            => mm_rst,
-      csr_mosi          => mm_mosi,        -- CSR = control status register
-      csr_miso          => mm_miso,
+      csr_mosi          => mac_mosi,       -- CSR = control status register
+      csr_miso          => mac_miso,
   
       -- ST
       tx_clk_312        => tx_ref_clk_312,
@@ -236,7 +234,7 @@ BEGIN
   PORT MAP (
     mm_init        => mm_init,
     total_header   => total_header,
-    clk_156        => rx_phy_clk_156,
+    rx_clk         => rx_phy_clk_156,
     rx_sosi        => rx_sosi,
     rx_siso        => rx_siso,
     rx_toggle      => rx_toggle
@@ -249,9 +247,9 @@ BEGIN
     g_pkt_length_arr => c_pkt_length_arr
   )
   PORT MAP (
-    tx_clk_156     => tx_ref_clk_156,
+    tx_clk         => tx_ref_clk_156,
     tx_sosi        => tx_sosi,
-    rx_clk_156     => rx_phy_clk_156,
+    rx_clk         => rx_phy_clk_156,
     rx_sosi        => rx_sosi
   );
     
@@ -260,9 +258,9 @@ BEGIN
     g_nof_pkt     => c_nof_pkt
   )
   PORT MAP (
-    tx_clk_156     => tx_ref_clk_156,
+    tx_clk         => tx_ref_clk_156,
     tx_sosi        => tx_sosi,
-    rx_clk_156     => rx_phy_clk_156,
+    rx_clk         => rx_phy_clk_156,
     rx_sosi        => rx_sosi,
     tx_pkt_cnt     => tx_pkt_cnt,
     rx_pkt_cnt     => rx_pkt_cnt,