-Changed generic g_nof_data_per_sync of mmp_st_histogram instance.

-node_sdp_adc_input_and_timing.vhd still compiles OK in QuestaSim.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -452,13 +452,12 @@ BEGIN
   -----------------------------------------------------------------------------
   -- ST Histogram
   -----------------------------------------------------------------------------
-
   u_st_histogram : ENTITY st_lib.mmp_st_histogram
   GENERIC MAP (
     g_nof_instances     => c_sdp_S_pn,
     g_data_w            => c_sdp_W_adc,
     g_nof_bins          => c_sdp_V_si_histogram,
-    g_nof_data_per_sync => 10**6 * c_sdp_f_adc_MHz
+    g_nof_data_per_sync => sel_a_b(g_sim, g_bsn_nof_clk_per_sync, c_sdp_f_adc_MHz*10**6 - c_sdp_N_fft/2)
   )
   PORT MAP (
     mm_rst            => mm_rst_internal,
@@ -473,9 +472,6 @@ BEGIN
   );
 
 
-
-
-
   -----------------------------------------------------------------------------
   -- Output Stage
   --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain