Expected multiplexer FIFO size.

applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt

@@ -90,6 +90,9 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
   . Write multiplexer for 12 + 1 = 13 inputs will take ~100 M20K,
     because it needs to multiplex and FIFO streams of 256 bit each and
     256 bit requires 256 /40 = 7 M20K in parallel, so 13 * 7 = 91 M20K.
+  . One M20K = 20b * 1024 words = 40b * 512 words, 512 words of 256b =
+    16 kByte, so FIFO can fit (almost) two 8 kB payloads, which seems
+    sufficient.
 
 Use 1 DDR4 module / FPGA
   . Because 16GB is enough for T_tbuf = 3.3 s