From a2933a2e13c2f09edf3c591df206bea7e78463c3 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 8 Feb 2023 15:22:27 +0100
Subject: [PATCH] Expected multiplexer FIFO size.
---
.../lofar2/doc/prestudy/station2_sdp_transient_buffer.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
index 779334661f..9b003c2d1e 100644
--- a/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt
@@ -90,6 +90,9 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
. Write multiplexer for 12 + 1 = 13 inputs will take ~100 M20K,
because it needs to multiplex and FIFO streams of 256 bit each and
256 bit requires 256 /40 = 7 M20K in parallel, so 13 * 7 = 91 M20K.
+ . One M20K = 20b * 1024 words = 40b * 512 words, 512 words of 256b =
+ 16 kByte, so FIFO can fit (almost) two 8 kB payloads, which seems
+ sufficient.
Use 1 DDR4 module / FPGA
. Because 16GB is enough for T_tbuf = 3.3 s
--
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