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Commit a1a8cea1 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added tb_arts_unb1_sc1_bf_offload;

-Added hex copy files line in hdllib.cfg
 . required for tb_arts_unb1_sc1_bf_offload.
parent d518591c
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hdl_lib_name = arts_unb1_sc1_bf_offload hdl_lib_name = arts_unb1_sc1_bf_offload
hdl_library_clause_name = arts_unb1_sc1_bf_offload_lib hdl_library_clause_name = arts_unb1_sc1_bf_offload_lib
hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
synth_files = synth_files =
src/vhdl/arts_offload_fifo.vhd src/vhdl/arts_offload_fifo.vhd
src/vhdl/mm_master.vhd src/vhdl/mm_master.vhd
...@@ -13,7 +14,7 @@ quartus_copy_files = ...@@ -13,7 +14,7 @@ quartus_copy_files =
src/hex hex src/hex hex
modelsim_copy_files = modelsim_copy_files =
src/hex hex ../../../apertif/designs/apertif_unb1_fn_bf_emu/src/hex/ hex
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
quartus_qsf_files = quartus_qsf_files =
......
-------------------------------------------------------------------------------
--
-- Copyright (C) 2016
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose:
-- . Feed 3 10GbE 'beamlet' streams to arts_unb1_sc1_bf_offload.
-- Description:
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, apertif_unb1_fn_bf_emu_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_arts_unb1_sc1_bf_offload IS
END tb_arts_unb1_sc1_bf_offload;
ARCHITECTURE tb OF tb_arts_unb1_sc1_bf_offload IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_xc_node_nr : NATURAL := 0; -- FN 0
CONSTANT c_xc_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_xc_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_bf_node_nr : NATURAL := 1; -- FN 1
CONSTANT c_bf_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_bf_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
SIGNAL XC_ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_xc_id;
SIGNAL BF_ID : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_bf_id;
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL bf_si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
------------------------------------------------------------------------------
-- fn_beamformer emulator (block generator -> 10GbE)
-- . we're instantiating this design once but copying its 10GbE output 3 times
-- to provide 3 10GbE inputs for the correlator FGPA.
------------------------------------------------------------------------------
u_apertif_unb1_fn_bf_emu : ENTITY apertif_unb1_fn_bf_emu_lib.apertif_unb1_fn_bf_emu
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_bf_node_nr
)
PORT MAP (
-- GENERAL
CLK => clk,
PPS => pps,
-- Others
VERSION => VERSION,
ID => BF_ID,
TESTIO => TESTIO,
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => '0',
-- Transceiver clocks
SA_CLK => sa_clk,
-- Serial I/O
SI_FN_0_TX => bf_si_fn_0_tx,
SI_FN_0_RX => (OTHERS => '0'),
SI_FN_1_RX => (OTHERS => '0'),
SI_FN_2_RX => (OTHERS => '0'),
SI_FN_3_RX => (OTHERS => '0')
);
------------------------------------------------------------------------------
-- ARTS SC1 beamformer
------------------------------------------------------------------------------
u_arts_unb1_sc1_bf_offload : ENTITY work.arts_unb1_sc1_bf_offload
GENERIC MAP (
g_sim => c_sim
)
PORT MAP (
-- GENERAL
CLK => clk,
PPS => pps,
-- Others
VERSION => VERSION,
ID => XC_ID,
TESTIO => TESTIO,
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => '0',
-- Transceiver clocks
SA_CLK => sa_clk,
SB_CLK => '0',
-- Serial I/O
SI_FN_0_RX => bf_si_fn_0_tx,
SI_FN_1_RX => bf_si_fn_0_tx,
SI_FN_2_RX => bf_si_fn_0_tx,
SI_FN_3_RX => (OTHERS => '0')
);
END tb;
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