First checkin of ARTS SC1 three dish, one polarisation design. Missing deinterleave.

applications/arts/designs/arts_unb1_sc1_bf_offload/hdllib.cfg

+hdl_lib_name = arts_unb1_sc1_bf_offload
+hdl_library_clause_name = arts_unb1_sc1_bf_offload_lib
+hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board 
+synth_files =
+    src/vhdl/arts_offload_fifo.vhd
+    src/vhdl/mm_master.vhd
+    src/vhdl/arts_unb1_sc1_bf_offload.vhd
+synth_top_level_entity =
+test_bench_files =
+    tb/vhdl/tb_arts_unb1_sc1_bf_offload.vhd
+quartus_copy_files =
+    quartus/qsys_mm_master.qsys .
+    src/hex hex
+
+modelsim_copy_files = 
+    src/hex hex
+
+hdl_lib_technology = ip_stratixiv
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/arts_unb1_sc1_bf_offload/qsys_mm_master/synthesis/qsys_mm_master.qip
+quartus_tcl_files =
+$RADIOHDL/applications/arts/designs/arts_unb1_sc1_bf_offload/quartus/pinning/arts_unb1_sc1_bf_offload_pins.tcl

applications/arts/designs/arts_unb1_sc1_bf_offload/quartus/pinning/arts_unb1_sc1_bf_offload_pins.tcl

+
+source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl

applications/arts/designs/arts_unb1_sc1_bf_offload/src/vhdl/arts_offload_fifo.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Wrapper containing dp_offload_tx and design-specific header fields
+-- Description:
+-- . 
+
+LIBRARY IEEE, common_lib, work, technology_lib, mm_lib, unb1_board_lib, dp_lib, tech_tse_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY  arts_offload_fifo IS
+  GENERIC (
+    g_technology         : NATURAL := c_tech_select_default;
+    g_nof_streams        : POSITIVE := 1;
+    g_nof_blocks         : NATURAL := 50;
+    g_nof_channels       : NATURAL := 24
+  ); 
+  PORT (
+    mm_rst                         : IN  STD_LOGIC;
+    mm_clk                         : IN  STD_LOGIC; 
+    
+    dp_rst                         : IN  STD_LOGIC;
+    dp_clk                         : IN  STD_LOGIC;  
+
+    reg_dp_offload_tx_hdr_dat_mosi : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+    snk_in                         : IN  t_dp_sosi;
+    snk_out                        : OUT t_dp_siso;
+
+    src_out_arr                    : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    src_in_arr                     : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+    ID                             : IN  STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)
+  );
+END  arts_offload_fifo;
+
+
+ARCHITECTURE wrap OF  arts_offload_fifo IS
+
+                                       -- Word align + Eth + IP + UDP + ID + Flags
+  CONSTANT c_nof_hdr_fields : NATURAL :=           1 +   3 + 12 +   4 +  6 + 8 ;    -- 34 fields
+                     -- Numer of bytes:            2 + <-----42-----> + 16 + 8*24/8 -- 2 + 42 + 40 = 84 bytes = 672 bits
+
+  CONSTANT c_hdr_field_arr  : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("word_align"                          ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("eth_dst_mac"                         ), "  ", 48, field_default(x"1418774428B8") ),
+                                                                                   ( field_name_pad("eth_src_mac"                         ), "  ", 48, field_default(0) ),
+                                                                                   ( field_name_pad("eth_type"                            ), "  ", 16, field_default(x"800") ),
+                                                                                   ( field_name_pad("ip_version"                          ), "  ",  4, field_default(4) ),
+                                                                                   ( field_name_pad("ip_header_length"                    ), "  ",  4, field_default(5) ),
+                                                                                   ( field_name_pad("ip_services"                         ), "  ",  8, field_default(0) ),
+                                                                                   ( field_name_pad("ip_total_length"                     ), "  ", 16, field_default(4868) ),
+                                                                                   ( field_name_pad("ip_identification"                   ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("ip_flags"                            ), "  ",  3, field_default(2) ),
+                                                                                   ( field_name_pad("ip_fragment_offset"                  ), "  ", 13, field_default(0) ),
+                                                                                   ( field_name_pad("ip_time_to_live"                     ), "  ",  8, field_default(127) ),
+                                                                                   ( field_name_pad("ip_protocol"                         ), "  ",  8, field_default(17) ),
+                                                                                   ( field_name_pad("ip_header_checksum"                  ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("ip_src_addr"                         ), "  ", 32, field_default(0) ),
+                                                                                   ( field_name_pad("ip_dst_addr"                         ), "  ", 32, field_default(x"0A63C82A") ),
+                                                                                   ( field_name_pad("udp_src_port"                        ), "  ", 16, field_default(4000) ), 
+                                                                                   ( field_name_pad("udp_dst_port"                        ), "  ", 16, field_default(4000) ), 
+                                                                                   ( field_name_pad("udp_total_length"                    ), "  ", 16, field_default(4848) ),
+                                                                                   ( field_name_pad("udp_checksum"                        ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("id_marker_byte"                      ), "  ",  8, field_default(65) ),
+                                                                                   ( field_name_pad("id_format_version"                   ), "  ",  8, field_default(1) ), 
+                                                                                   ( field_name_pad("id_source_id"                        ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("id_n_channels"                       ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("id_n_blocks"                         ), "  ", 16, field_default(0) ),
+                                                                                   ( field_name_pad("id_timestamp"                        ), "  ", 64, field_default(0) ),
+                                                                                   ( field_name_pad("flags_crc_error"                     ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_no_input_present"              ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_uploading_weights"             ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_noise_source_enabled"          ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_telescope_pointing_off"        ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_antenna_broken"                ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_reserved_0"                    ), "  ", 24, field_default(0) ),
+                                                                                   ( field_name_pad("flags_reserved_1"                    ), "  ", 24, field_default(0) ) ); 
+
+  CONSTANT c_hdr_field_sel         : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0)  :=             "1101" &  -- Eth header fields: eth_src_mac from data path (others use MM default value).
+                                                                                           "111111111101" &  -- IP  header fields: ip_src_addr from data path (others use MM default value).
+                                                                                                   "1111" &  -- UDP header fields
+                                                                                                 "110000" &  -- ID  header fields: MM controlled: marker byte, format version. From data path: source ID, n_channels, n_blocks and timestamp.
+                                                                                               "00111111";   -- Flag fields: crc_error and no_input_present from data path, others via MM.
+
+  CONSTANT c_nof_hdr_words              : NATURAL := field_slv_len(c_hdr_field_arr)/c_tech_tse_data_w;
+
+  CONSTANT c_bsn_w                      : NATURAL := 64;
+
+
+  CONSTANT c_nof_words_per_block        : NATURAL := 1200;
+  CONSTANT c_nof_blocks_per_packet      : NATURAL := 1;
+  CONSTANT c_fifo_size                  : NATURAL := 4096;
+ 
+  SIGNAL dp_fifo_sc_snk_in_arr          : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL dp_fifo_sc_snk_out_arr         : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+  SIGNAL dp_fifo_sc_src_out_arr         : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL dp_fifo_sc_src_in_arr          : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+  SIGNAL dp_offload_tx_src_out_arr      : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL dp_offload_tx_src_in_arr       : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+  SIGNAL hdr_fields_in_arr              : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL id_backplane                   : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+  SIGNAL id_chip                        : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+
+BEGIN
+
+  --------------------------------------------------------------------------------------- 
+  -- Swap the bytes in the 32b words to make them little-endian
+  ---------------------------------------------------------------------------------------
+  p_connect : PROCESS(snk_in)
+  BEGIN
+    -- Control
+    dp_fifo_sc_snk_in_arr(0)                                      <= snk_in;
+    -- Data: re&im concatenated so real part is put on the line first: re,im,re,im, ..
+    dp_fifo_sc_snk_in_arr(0).data(  c_byte_w-1 DOWNTO          0) <= snk_in.data(4*c_byte_w-1 DOWNTO 3*c_byte_w);
+    dp_fifo_sc_snk_in_arr(0).data(2*c_byte_w-1 DOWNTO   c_byte_w) <= snk_in.data(3*c_byte_w-1 DOWNTO 2*c_byte_w);
+    dp_fifo_sc_snk_in_arr(0).data(3*c_byte_w-1 DOWNTO 2*c_byte_w) <= snk_in.data(2*c_byte_w-1 DOWNTO   c_byte_w);
+    dp_fifo_sc_snk_in_arr(0).data(4*c_byte_w-1 DOWNTO 3*c_byte_w) <= snk_in.data(  c_byte_w-1 DOWNTO          0);
+  END PROCESS;
+
+  --------------------------------------------------------------------------------------- 
+  -- FIFO
+  ---------------------------------------------------------------------------------------
+  snk_out <= dp_fifo_sc_snk_out_arr(0);
+
+  u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+  GENERIC MAP(
+    g_technology => g_technology,
+    g_data_w     => c_tech_tse_data_w,
+    g_bsn_w      => c_bsn_w,
+    g_fifo_size  => c_fifo_size,
+    g_use_bsn    => TRUE,
+    g_use_ctrl   => TRUE
+  )
+  PORT MAP (
+    rst          => dp_rst,
+    clk          => dp_clk,
+
+    snk_out      => dp_fifo_sc_snk_out_arr(0),
+    snk_in       => dp_fifo_sc_snk_in_arr(0),
+
+    src_in       => dp_fifo_sc_src_in_arr(0),
+    src_out      => dp_fifo_sc_src_out_arr(0)
+  );
+
+  --------------------------------------------------------------------------------------- 
+  -- dp_offload_tx
+  ---------------------------------------------------------------------------------------
+  u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
+  GENERIC MAP (
+    g_technology                => g_technology,
+    g_nof_streams               => g_nof_streams,
+    g_data_w                    => c_tech_tse_data_w,
+    g_use_complex               => FALSE,
+    g_nof_words_per_block       => c_nof_words_per_block,
+    g_nof_blocks_per_packet     => c_nof_blocks_per_packet,
+    g_hdr_field_arr             => c_hdr_field_arr,
+    g_hdr_field_sel             => c_hdr_field_sel
+   )
+  PORT MAP (
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+    
+    dp_rst                => dp_rst,
+    dp_clk                => dp_clk,
+
+    reg_hdr_dat_mosi      => reg_dp_offload_tx_hdr_dat_mosi,
+    reg_hdr_dat_miso      => reg_dp_offload_tx_hdr_dat_miso,
+
+    snk_in_arr            => dp_fifo_sc_src_out_arr,
+    snk_out_arr           => dp_fifo_sc_src_in_arr,
+
+    src_out_arr           => dp_offload_tx_src_out_arr,
+    src_in_arr            => dp_offload_tx_src_in_arr,
+
+    hdr_fields_in_arr     => hdr_fields_in_arr
+  );
+
+  src_out_arr              <= dp_offload_tx_src_out_arr;
+  dp_offload_tx_src_in_arr <= src_in_arr;
+
+  --------------------------------------------------------------------------------------- 
+  -- Extract the backplane number from ID
+  ---------------------------------------------------------------------------------------
+  id_backplane <= RESIZE_UVEC(ID(7 DOWNTO 3), c_byte_w);
+  id_chip      <= RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+  --------------------------------------------------------------------------------------- 
+  -- Assign DP record fields and ID to header fields
+  ---------------------------------------------------------------------------------------
+  gen_slv_hard_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac"        ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac"       )) <= x"00228608" & id_backplane & id_chip;
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port"       ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port"      )) <= x"D0" & ID;
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port"       ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port"      )) <= x"D0" & ID;
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr"        ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr"       )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
+
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_source_id"       ) DOWNTO field_lo(c_hdr_field_arr, "id_source_id"      )) <= x"00" & id_backplane;
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_n_channels"      ) DOWNTO field_lo(c_hdr_field_arr, "id_n_channels"     )) <= TO_UVEC(g_nof_channels, c_halfword_w);
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_n_blocks"        ) DOWNTO field_lo(c_hdr_field_arr, "id_n_blocks"       )) <= TO_UVEC(g_nof_blocks, c_halfword_w);
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_timestamp"       ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp"      )) <= dp_fifo_sc_src_out_arr(0).bsn;
+  END GENERATE;
+
+END wrap;