modify header

libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd

@@ -24,15 +24,16 @@
 --   number
 -- Description:
 --   When dp_on is low then all outputs are low. When dp_on is high, the 
---   output sync starts pulsing with a period of g_block_size number of clk 
---   cycles and the output valid, sop and eop will be active.
+--   output sync starts pulsing after bsn_time_offset (in clk cycles) with 
+--   a period of g_block_size number of clk cycles and the output valid, 
+--   sop and eop will be active.
 --   Alternatively, one can assert dp_on while dp_on_pps is high to 
 --   start the data path on the next PPS.
 -- Remarks:
 --   Starting the data path is only possible from the dp_off state, so one
 --   has to disable (dp_on='0') the data path before restarting it.
 --
+-- author : P.Donker  okt. 2020, added bsn_time_offset
 --
 
 LIBRARY IEEE, common_lib;