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Commit 41fc4776 authored by Pieter Donker's avatar Pieter Donker
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add mm-bus control for bsn_time_offset and add test to tb_mms_

parent 16941063
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3 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!54Resolve L2SDP-49,!49WIP: Resolve L2SDP-49
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libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+ 70
− 16
View file @ 41fc4776
......@@ -36,6 +36,7 @@
-- 1 [31..0] WR nof_clk_per_sync 0x0
-- 2 [31..0] RW bsn[31..0] 0x0 write bsn_init, read current bsn
-- 3 [31..0] RW bsn[63..32] 0x0 write bsn_init, read current bsn
-- 4 [31..0] RW bsn_time_offset 0x0
-- ====================================================================================
LIBRARY IEEE, common_lib;
......@@ -65,7 +66,9 @@ ENTITY dp_bsn_source_reg_v2 IS
st_on_status : IN STD_LOGIC;
st_nof_clk_per_sync : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- nof block per sync
st_bsn_init : OUT STD_LOGIC_VECTOR; -- wr init BSN
st_current_bsn : IN STD_LOGIC_VECTOR -- rd current BSN
st_current_bsn : IN STD_LOGIC_VECTOR; -- rd current BSN
st_bsn_time_offset : OUT STD_LOGIC_VECTOR;
st_current_bsn_time_offset : IN STD_LOGIC_VECTOR
);
END dp_bsn_source_reg_v2;
......@@ -73,12 +76,13 @@ END dp_bsn_source_reg_v2;
ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
CONSTANT c_bsn_w : NATURAL := st_bsn_init'LENGTH;
CONSTANT c_bsn_time_offset_w : NATURAL := st_bsn_time_offset'LENGTH;
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
adr_w => 3,
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 2**2,
nof_dat => 3**2,
init_sl => '0');
-- Registers in mm_clk domain
......@@ -95,6 +99,10 @@ ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
SIGNAL mm_current_bsn : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_current_bsn_hi : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_bsn_time_offset_wr : STD_LOGIC;
SIGNAL mm_current_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Registers in st_clk domain
BEGIN
......@@ -119,12 +127,15 @@ BEGIN
mm_bsn_init <= (OTHERS=>'0');
mm_bsn_init_wr <= '0';
mm_current_bsn_hi <= (OTHERS=>'0');
mm_bsn_time_offset <= (OTHERS=>'0');
mm_bsn_time_offset_wr <= '0';
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
sla_out.rdval <= '0';
-- Access event defaults
mm_bsn_init_wr <= '0';
mm_bsn_time_offset_wr <= '0';
-- Write access: set register value
IF sla_in.wr = '1' THEN
......@@ -143,6 +154,11 @@ BEGIN
mm_bsn_init(63 DOWNTO 32) <= sla_in.wrdata(31 DOWNTO 0);
mm_bsn_init_wr <= '1';
-- write bsn_time_offset
WHEN 4 =>
mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= sla_in.wrdata(c_bsn_time_offset_w-1 DOWNTO 0);
mm_bsn_time_offset_wr <= '1';
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
......@@ -165,6 +181,10 @@ BEGIN
WHEN 3 =>
sla_out.rddata(31 DOWNTO 0) <= mm_current_bsn_hi;
-- Read current bsn_time_offset
WHEN 4 =>
sla_out.rddata(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0);
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
......@@ -193,19 +213,25 @@ BEGIN
st_on_pps <= mm_on_pps;
st_nof_clk_per_sync <= mm_nof_clk_per_sync;
st_bsn_init <= mm_bsn_init(c_bsn_w-1 DOWNTO 0);
st_bsn_time_offset <= mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0);
p_st_clk : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst='1' THEN
st_bsn_init <= TO_UVEC(0, c_bsn_w);
st_bsn_time_offset <= TO_UVEC(0, c_bsn_time_offset_w);
ELSIF rising_edge(st_clk) THEN
IF mm_bsn_init_wr='1' THEN
st_bsn_init <= mm_bsn_init(c_bsn_w-1 DOWNTO 0); -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
END IF;
IF mm_bsn_time_offset_wr='1' THEN
st_bsn_time_offset <= mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0); -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
END IF;
END IF;
END PROCESS;
mm_current_bsn(c_bsn_w-1 DOWNTO 0) <= st_current_bsn; -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= st_current_bsn_time_offset;
END GENERATE; -- no_cross
gen_cross : IF g_cross_clock_domain = TRUE GENERATE
......@@ -280,6 +306,34 @@ BEGIN
out_new => OPEN
);
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_time_offset : ENTITY common_lib.common_reg_cross_domain
PORT MAP (
in_rst => mm_rst,
in_clk => mm_clk,
in_new => mm_bsn_time_offset_wr, -- use wr of mm_bsn_time_offset high part for in_new to ensure proper transfer of double word
in_dat => mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0),
in_done => OPEN, -- pulses when no more pending in_new
out_rst => st_rst,
out_clk => st_clk,
out_dat => st_bsn_time_offset,
out_new => OPEN
);
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_current_bsn_offset : ENTITY common_lib.common_reg_cross_domain
PORT MAP (
in_rst => st_rst,
in_clk => st_clk,
in_new => '1',
in_dat => st_current_bsn_time_offset,
in_done => OPEN, -- pulses when no more pending in_new
out_rst => mm_rst,
out_clk => mm_clk,
out_dat => mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0),
out_new => OPEN
);
END GENERATE; -- gen_cross
END rtl;
libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+ 33
− 25
View file @ 41fc4776
......@@ -46,7 +46,7 @@ ENTITY dp_bsn_source_v2 IS
g_block_size : NATURAL := 256;
g_nof_clk_per_sync : NATURAL := 200 * 10**6;
g_bsn_w : NATURAL := 48;
g_time_offset_w : NATURAL := 10
g_bsn_time_offset_w : NATURAL := 10
);
PORT (
rst : IN STD_LOGIC;
......@@ -60,7 +60,8 @@ ENTITY dp_bsn_source_v2 IS
bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_time_offset : IN STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
bsn_time_offset : IN STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
current_bsn_time_offset : OUT STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
src_out : OUT t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
);
......@@ -101,8 +102,11 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_dp_on_status : STD_LOGIC;
SIGNAL nxt_dp_on_status : STD_LOGIC;
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0);
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL i_current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL nxt_current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL nxt_clk_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL clk_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
......@@ -113,8 +117,9 @@ BEGIN
src_out <= i_src_out;
dp_on_status <= i_dp_on_status;
current_bsn_time_offset <= i_current_bsn_time_offset;
p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, clk_cnt, bsn_init, i_src_out, i_dp_on_status, bsn_time_offset_cnt)
p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, clk_cnt, bsn_init, i_src_out, i_dp_on_status, bsn_time_offset_cnt, bsn_time_offset)
BEGIN
nxt_state <= state;
nxt_src_out <= i_src_out;
......@@ -127,6 +132,8 @@ BEGIN
nxt_sync <= sync;
nxt_dp_on_status <= i_dp_on_status;
nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
nxt_current_bsn_time_offset <= bsn_time_offset;
IF UNSIGNED(clk_cnt) = UNSIGNED(nof_clk_per_sync) - 1 THEN
nxt_clk_cnt <= (OTHERS=>'0');
......@@ -224,6 +231,7 @@ BEGIN
block_size_cnt <= nxt_block_size_cnt;
i_dp_on_status <= nxt_dp_on_status;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
END IF;
END PROCESS;
......
libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+ 30
− 23
View file @ 41fc4776
......@@ -34,7 +34,8 @@ ENTITY mms_dp_bsn_source_v2 IS
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_block_size : NATURAL := 256; -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
g_nof_clk_per_sync : NATURAL := 200 * 10**6; -- ;
g_bsn_w : NATURAL := 48
g_bsn_w : NATURAL := 48;
g_bsn_time_offset_w : NATURAL := 10
);
PORT (
-- Clocks and reset
......@@ -60,12 +61,14 @@ ARCHITECTURE str OF mms_dp_bsn_source_v2 IS
SIGNAL dp_on_pps : STD_LOGIC;
SIGNAL nof_clk_per_sync : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL bsn_init : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
SIGNAL bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL i_bs_sosi : t_dp_sosi;
SIGNAL dp_on_status : STD_LOGIC;
SIGNAL capture_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
BEGIN
......@@ -93,7 +96,9 @@ BEGIN
st_on_status => dp_on_status,
st_nof_clk_per_sync => nof_clk_per_sync,
st_bsn_init => bsn_init,
st_current_bsn => capture_bsn
st_current_bsn => capture_bsn,
st_bsn_time_offset => bsn_time_offset,
st_current_bsn_time_offset => current_bsn_time_offset
);
u_bsn_source : ENTITY work.dp_bsn_source_v2
......@@ -112,6 +117,8 @@ BEGIN
dp_on_status => dp_on_status,
bsn_init => bsn_init,
nof_clk_per_sync => nof_clk_per_sync,
bsn_time_offset => bsn_time_offset,
current_bsn_time_offset => current_bsn_time_offset,
-- Streaming
src_out => i_bs_sosi
);
......
libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+ 25
− 1
View file @ 41fc4776
......@@ -44,6 +44,8 @@ END tb_mms_dp_bsn_source_v2;
ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
CONSTANT c_bsn_time_offset_w : NATURAL := 10;
CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_pps_interval : NATURAL := 1000;
......@@ -58,6 +60,7 @@ ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
CONSTANT c_mm_addr_nof_block_per_sync : NATURAL := 1;
CONSTANT c_mm_addr_bsn_lo : NATURAL := 2;
CONSTANT c_mm_addr_bsn_hi : NATURAL := 3;
CONSTANT c_mm_addr_bsn_time_offset : NATURAL := 4;
CONSTANT c_mm_dp_off : NATURAL := 0; -- DP off after finishing current block
CONSTANT c_mm_dp_on_immediate : NATURAL := 1; -- DP on immediate by setting bit 0
......@@ -74,6 +77,8 @@ ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
SIGNAL mm_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_bsn_prev : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL mm_miso : t_mem_miso;
......@@ -114,7 +119,7 @@ BEGIN
ASSERT mm_dp_on_status=c_mm_dp_on_immediate REPORT "Wrong DP on status, expected DP on immediate." SEVERITY ERROR;
-- Read BSN twice in same PPS interval
proc_common_wait_some_cycles(clk, 3*c_block_size);
proc_common_wait_some_cycles(clk, c_block_size);
proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
......@@ -152,6 +157,25 @@ BEGIN
proc_common_wait_some_cycles(clk, 1);
ASSERT mm_dp_on_status=c_mm_dp_off REPORT "Wrong DP on status, expected DP off." SEVERITY ERROR;
-- Set bsn_time_offset and read back 2 times 0 and 5
proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 0, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, 2*c_cross_clock_domain_latency);
proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_miso.rddata(c_bsn_time_offset_w-1 DOWNTO 0);
proc_common_wait_some_cycles(clk, 1);
ASSERT TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0))=0 REPORT "Wrong offset, expected 0" SEVERITY ERROR;
proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 5, clk, mm_miso, mm_mosi);
proc_common_wait_some_cycles(clk, 2*c_cross_clock_domain_latency);
proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_miso.rddata(c_bsn_time_offset_w-1 DOWNTO 0);
proc_common_wait_some_cycles(clk, 1);
ASSERT TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0))=5 REPORT "Wrong offset, expected 5" SEVERITY ERROR;
proc_common_wait_some_cycles(clk, c_sync_interval);
tb_end <= '1';
WAIT;
......
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