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applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd

@@ -47,8 +47,7 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
   CONSTANT  c_data_w          : NATURAL         := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- 576
   CONSTANT  c_adr_w           : NATURAL         := 4;
   CONSTANT  c_max_adr         : NATURAL         := 2**c_adr_w;
-            k
-            k
+
   SIGNAL    tb_end            : STD_LOGIC       := '0';
 
   SIGNAL    clk               : STD_LOGIC       := '1';
@@ -62,11 +61,15 @@ ARCHITECTURE tb OF tb_ddrctrl_address_counter IS
 
 BEGIN
 
-  in_sosi.data(c_data_w - 1 DOWNTO 0)    <= in_data(c_data_w - 1 DOWNTO 0);
-  in_sosi.valid                          <= in_data_enable;
-
+  -- if these ASSERT's get uncommented u can see that modelsim does take a few itteration before the warning gets asserted. These asserts are also present in p_verify
 
+  --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata"  SEVERITY ERROR;   -- gives error if in_sosi and out_mosi do not match
+  --ASSERT in_sosi.valid                       = out_mosi.wr                            REPORT "in_sosi.valid does not match out_mosi.wr"      SEVERITY ERROR;
+  --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) /= out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does match out_mosi.wrdata"  SEVERITY WARNING;    -- gives warning if in_sosi and out_mosi do match
+  --ASSERT in_sosi.valid                       /= out_mosi.wr                            REPORT "in_sosi.valid does match out_mosi.wr"      SEVERITY WARNING;
 
+  in_sosi.data(c_data_w - 1 DOWNTO 0)    <= in_data(c_data_w - 1 DOWNTO 0);
+  in_sosi.valid                          <= in_data_enable;
 
   clk <= NOT clk OR tb_end AFTER c_clk_period/2;
 
@@ -82,13 +85,10 @@ BEGIN
     WAIT UNTIL rising_edge(clk);  -- align to rising edge
     WAIT FOR c_clk_period*10;
 
-    ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "Wrong wrdata 1"  SEVERITY ERROR;
-    ASSERT in_sosi.valid                       = out_mosi.wr                            REPORT "Wrong wr 1"      SEVERITY ERROR;
-
     FOR I IN 0 TO 6 LOOP
       in_data_enable  <= '1';
       in_data         <= NOT in_data;
-      ASSERT I                                 = TO_UINT(out_mosi.address)              REPORT "Wrong address 1" SEVERITY ERROR;
+      ASSERT I                                 = TO_UINT(out_mosi.address)              REPORT "Wrong address, I = " & NATURAL'image(I) SEVERITY ERROR;
       WAIT FOR c_clk_period*1;
       in_data_enable  <= '0';
       WAIT FOR c_clk_period*2;
@@ -112,8 +112,19 @@ BEGIN
     WAIT FOR c_clk_period*20;
 
     tb_end            <= '1';
-
     WAIT;
+
+  END PROCESS;
+
+  p_verify : PROCESS
+  BEGIN
+    WAIT UNTIL rising_edge(clk);
+    IF rising_edge(clk) THEN
+      ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) = out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does not match out_mosi.wrdata"  SEVERITY ERROR;   -- gives error if in_sosi and out_mosi do not match
+      ASSERT in_sosi.valid                       = out_mosi.wr                            REPORT "in_sosi.valid does not match out_mosi.wr"      SEVERITY ERROR;
+      --ASSERT in_sosi.data(c_data_w - 1 DOWNTO 0) /= out_mosi.wrdata(c_data_w - 1 DOWNTO 0) REPORT "in_sosi.data does match out_mosi.wrdata"  SEVERITY WARNING;    -- gives warning if in_sosi and out_mosi do match
+      --ASSERT in_sosi.valid                       /= out_mosi.wr                            REPORT "in_sosi.valid does match out_mosi.wr"      SEVERITY WARNING;
+    END IF;
   END PROCESS;
 
   u_address_counter : ENTITY work.ddrctrl_address_counter