From a069296e0a2782fabe4b0337fe96909fd5062ee7 Mon Sep 17 00:00:00 2001 From: Eric Kooistra <kooistra@astron.nl> Date: Thu, 24 Nov 2022 09:27:31 +0100 Subject: [PATCH] Avoid no driver warning in synthesis. --- libraries/base/dp/src/vhdl/dp_fifo_core.vhd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd index 083fd11c10..c8f9cb39db 100644 --- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd +++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd @@ -111,7 +111,7 @@ ARCHITECTURE str OF dp_fifo_core IS SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0); SIGNAL fifo_wr_req : STD_LOGIC; SIGNAL fifo_wr_ful : STD_LOGIC; - SIGNAL wr_init : STD_LOGIC := '0'; + SIGNAL wr_init : STD_LOGIC := '0'; SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE); SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0'); @@ -191,6 +191,7 @@ BEGIN usedw => fifo_rd_usedw ); + wr_init <= '0'; -- to avoid no driver warning in synthesis fifo_wr_usedw <= fifo_rd_usedw; END GENERATE; -- GitLab