tr_xaui_mdio is now instantiated as component to fix compile errors when

compiling for unb2

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -159,6 +159,36 @@ ARCHITECTURE str OF tr_10GbE IS
   SIGNAL dp_fifo_dc_rx_src_out_arr      : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); 
   SIGNAL dp_fifo_dc_rx_src_in_arr       : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
 
+
+  COMPONENT tr_xaui_mdio IS
+  GENERIC (
+    g_sim                   : BOOLEAN := FALSE;
+    g_nof_xaui              : NATURAL := 1;     -- Up to 3 (hard XAUI only) supported
+    g_mdio_epcs_dis         : BOOLEAN := FALSE -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it 
+  );
+  PORT (   
+    -- Transceiver PLL reference clock   
+    tr_clk                  : IN  STD_LOGIC;
+    tr_rst                  : IN  STD_LOGIC;
+
+    -- MM clock for register of optional MDIO master
+    mm_clk                  : IN  STD_LOGIC := '0';
+    mm_rst                  : IN  STD_LOGIC := '0';
+
+    -- MDIO master = mm slave
+    mdio_mosi_arr           : IN  t_mem_mosi_arr(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
+    mdio_miso_arr           : OUT t_mem_miso_arr(g_nof_xaui-1 DOWNTO 0);
+
+    -- MDIO External clock and serial data.
+    mdio_rst                : OUT STD_LOGIC;
+    mdio_mdc_arr            : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0);       
+    mdio_mdat_in_arr        : IN  STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0) := (OTHERS=>'0');
+    mdio_mdat_oen_arr       : OUT STD_LOGIC_VECTOR(g_nof_xaui-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+
+
 BEGIN
 
   ---------------------------------------------------------------------------------------
@@ -297,7 +327,7 @@ BEGIN
   -- MDIO
   ---------------------------------------------------------------------------
   gen_mdio: IF g_use_mdio = TRUE GENERATE
-    u_tr_xaui_mdio : ENTITY tr_xaui_lib.tr_xaui_mdio
+    u_tr_xaui_mdio : tr_xaui_mdio --ENTITY tr_xaui_lib.tr_xaui_mdio
     GENERIC MAP (
       g_sim           => g_sim,
       g_nof_xaui      => g_nof_macs,