testbench should be skipped when the seleted technology is not stratixiv

libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd

@@ -48,12 +48,13 @@ BEGIN
   u_tech : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 0) PORT MAP (tb_end_vec(0));
   u_sim  : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 1) PORT MAP (tb_end_vec(1));
   
-  tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+  tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec OR c_tech_select_default /= c_tech_stratixiv  ELSE '0';
   
   p_tb_end : PROCESS
   BEGIN
     WAIT UNTIL tb_end='1';
-    WAIT FOR 1 ns;
+    ASSERT (c_tech_select_default = c_tech_stratixiv) REPORT "Technology is not stratixiv, skipping testbench..." SEVERITY WARNING;
+    WAIT FOR 1 ms;
     REPORT "Multi tb simulation finished." SEVERITY FAILURE;
     WAIT;
   END PROCESS;