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Commit 9f68afec authored by Reinier van der Walle's avatar Reinier van der Walle
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fixed compile errors

parent 0162c901
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1 merge request!191Resolve L2SDP-291
Pipeline #23642 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+ 5
− 5
View file @ 9f68afec
......@@ -29,7 +29,7 @@
-- .
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
......@@ -105,7 +105,7 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL local_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL ring_mux_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL rx_sosi_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL rx_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL dispatch_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL crosslets_sosi : t_dp_sosi := c_dp_sosi_rst;
......@@ -194,7 +194,7 @@ BEGIN
GENERIC MAP (
g_bsn_w => c_dp_stream_bsn_w,
g_data_w => c_longword_w,
g_in_chanel_w => c_word_w,
g_channel_w => c_word_w,
g_use_error => FALSE,
g_fifo_size => array_init(c_block_size, 2)
)
......@@ -334,9 +334,9 @@ BEGIN
mm_clk => mm_clk,
master_mosi_arr => controller_copi_arr,
master_cipo_arr => controller_cipo_arr,
master_miso_arr => controller_cipo_arr,
mux_mosi => controller_mem_mux_copi,
mux_cipo => controller_mem_mux_cipo
mux_miso => controller_mem_mux_cipo
);
---------------------------------------------------------------
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+ 13
− 5
View file @ 9f68afec
......@@ -26,7 +26,7 @@
-- Combines sdp nodes. Contains the UniBoard2 HW version independent LOFAR2 SDP application code.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, nw_10gbe_lib, eth_lib, ring_lib;
LIBRARY IEEE, common_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, tr_10gbe_lib, nw_10gbe_lib, eth_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
......@@ -362,7 +362,7 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_nof_mac : NATURAL := 3; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
SIGNAL gn_index : NATURAL := 0;
SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
----------------------------------------------
-- BF
----------------------------------------------
......@@ -406,6 +406,13 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL xst_from_ri_sosi : t_dp_sosi;
SIGNAL xst_to_ri_sosi : t_dp_sosi;
SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
SIGNAL dp_bsn_source_restart : STD_LOGIC;
SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
......@@ -417,6 +424,8 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL tr_ref_clk_156 : STD_LOGIC;
SIGNAL tr_ref_rst_156 : STD_LOGIC;
SIGNAL tr_10gbe_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL nw_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL nw_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
......@@ -498,7 +507,6 @@ BEGIN
ring_info => ring_info
);
gn_index <= TO_UINT(ID);
this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) WHEN rising_edge(dp_clk); -- Using register to ease timing closure.
-----------------------------------------------------------------------------
......@@ -714,7 +722,7 @@ BEGIN
-- QSFP_RX
lane_rx_cable_sosi_arr(0) <= tr_10gbe_src_out_arr(c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
-- QSFP_TX
tr_10gbe_snk_in_arr(c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(0) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst -- use_cable_to_next_rn=1 -> even lanes transmit to cable
tr_10gbe_snk_in_arr(c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(0) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> even lanes transmit to cable
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_sosi_arr(0) <= tr_10gbe_src_out_arr(c_ring_0_if_offset);
......
libraries/base/ring/src/vhdl/ring_mux.vhd
+ 7
− 7
View file @ 9f68afec
......@@ -39,7 +39,7 @@ ENTITY ring_mux IS
g_bsn_w : NATURAL := 16;
g_data_w : NATURAL := 16;
g_empty_w : NATURAL := 1;
g_in_channel_w : NATURAL := 1;
g_channel_w : NATURAL := 1;
g_error_w : NATURAL := 1;
g_use_bsn : BOOLEAN := TRUE;
g_use_empty : BOOLEAN := TRUE;
......@@ -59,7 +59,7 @@ ENTITY ring_mux IS
local_siso : OUT t_dp_siso;
mux_sosi : OUT t_dp_sosi;
mux_siso : IN t_dp_siso := c_dp_siso_rdy;
mux_siso : IN t_dp_siso := c_dp_siso_rdy
);
END ring_mux;
......@@ -97,13 +97,13 @@ BEGIN
)
PORT MAP (
dp_rst => dp_rst,
dp_clk => dp_clk,
rst => dp_rst,
clk => dp_clk,
snk_out_arr => dp_mux_in_siso_arr;
snk_in_arr => dp_mux_in_sosi_arr;
snk_out_arr => dp_mux_in_siso_arr,
snk_in_arr => dp_mux_in_sosi_arr,
src_in => mux_siso;
src_in => mux_siso,
src_out => mux_sosi
);
......
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