Add tbs to regression test; wg and aduh array versions use mms_*

applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg

@@ -15,6 +15,8 @@ test_bench_files =
     tb/vhdl/tb_lofar2_unb2b_adc.vhd
     tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
 
+regression_test_vhdl =
+    tb/vhdl/tb_lofar2_unb2b_adc.vhd
 
 [modelsim_project_file]
 modelsim_copy_files = 

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg

@@ -14,11 +14,12 @@ hdl_lib_technology = ip_arria10_e1sg
 test_bench_files = 
     tb_lofar2_unb2b_adc_full.vhd
 
+regression_test_vhdl =
+    tb_lofar2_unb2b_adc_full.vhd
 
 
 [modelsim_project_file]
 modelsim_copy_files =
-# Pinning design only intended for synthesis
 
 
 [quartus_project_file]

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd

@@ -18,6 +18,13 @@
 --
 -------------------------------------------------------------------------------
 
+-- Author : J Hargreaves
+-- Purpose:  
+--   Wrapper for full adc input test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 12 ADC streams
+
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -32,7 +39,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY lofar2_unb2b_adc_full IS
   GENERIC (
     g_design_name      : STRING  := "lofar2_unb2b_adc_full";
-    g_design_note      : STRING  := "Lofar2 adc with one node";
+    g_design_note      : STRING  := "Lofar2 adc with all streams";
     g_sim              : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr       : NATURAL := 0;
     g_sim_node_nr      : NATURAL := 0;

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg

@@ -14,6 +14,8 @@ hdl_lib_technology = ip_arria10_e1sg
 test_bench_files = 
     tb_lofar2_unb2b_adc_one_node.vhd
 
+regression_test_vhdl =
+    tb_lofar2_unb2b_adc_one_node.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd

@@ -19,6 +19,13 @@
 -------------------------------------------------------------------------------\
 
 
+-- Author : J Hargreaves
+-- Purpose:  
+--   Wrapper for one node adc input test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 1 ADC stream
+
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd

@@ -43,8 +43,9 @@ ENTITY node_adc_input_and_timing IS
     g_technology              : NATURAL := c_tech_arria10_e1sg;
     g_buf_nof_data            : NATURAL := 1024;
     g_nof_streams             : NATURAL := 12;
-    g_nof_sync_n              : NATURAL := 4;     -- Three ADCs per RCU share a sync
-    g_aduc_buffer_nof_symbols : NATURAL := 512;   -- Default 512
+    g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
+    g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
+    g_bsn_sync_timeout        : NATURAL := 200000000;  -- Default 200M, overide for short simulation 
     g_sim                     : BOOLEAN := FALSE  
   );
   PORT (
@@ -162,14 +163,6 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
   SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
 
 
-  -------------------------------------------------------------------------------
-  -- DP sync checker / insert
-  -------------------------------------------------------------------------------
-  CONSTANT c_nof_clk_per_blk        : NATURAL := 1024;
-  CONSTANT c_nof_blk_per_sync       : NATURAL := 800000;
-  CONSTANT c_nof_clk_per_sync       : NATURAL := c_nof_blk_per_sync * 256;  -- = 800000 * 256
-  CONSTANT c_bsn_sync_timeout       : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin
-
 BEGIN
 
   -----------------------------------------------------------------------------
@@ -415,7 +408,7 @@ BEGIN
   u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
   GENERIC MAP (
     g_nof_streams        => 1,  -- They're all the same
-    g_sync_timeout       => c_bsn_sync_timeout,
+    g_sync_timeout       => g_bsn_sync_timeout,
     g_bsn_w              => c_bs_bsn_w,
     g_log_first_bsn      => FALSE
   )
@@ -429,7 +422,6 @@ BEGIN
     -- Streaming clock domain
     dp_rst      => rx_rst,
     dp_clk      => rx_clk,
-    in_siso_arr => (OTHERS=>c_dp_siso_rdy),
     in_sosi_arr => st_sosi_arr(0 downto 0)
   );
 
@@ -444,7 +436,7 @@ BEGIN
     g_symbol_w             => c_data_w,   --TBD 16?
     g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
     g_nof_accumulations    => 200000512,  -- = 195313 blocks * 1024 samples
-    g_buffer_nof_symbols   => g_aduc_buffer_nof_symbols,  -- default 512, larger for full design
+    g_buffer_nof_symbols   => g_aduh_buffer_nof_symbols,  -- default 512, larger for full design
     g_buffer_use_sync      => TRUE        -- True to capture all streams synchronously
   )
   PORT MAP (

libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd

@@ -72,11 +72,6 @@ ENTITY mms_diag_wg_wideband_arr IS
     st_restart           : IN  STD_LOGIC := '0';
 
     out_sosi_arr         : OUT  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
-
---    out_ovr              : OUT STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0);  -- big endian, so first output sample in MSBit, MSData
---    out_dat              : OUT STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
---    out_val              : OUT STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0);
---    out_sync             : OUT STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0)
   );
 END mms_diag_wg_wideband_arr;
 
@@ -86,7 +81,6 @@ ARCHITECTURE str OF mms_diag_wg_wideband_arr IS
   CONSTANT c_reg_adr_w    : NATURAL := ceil_log2(2);
   CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(10);
     
-  SIGNAL st_wg_ctrl_arr   : t_diag_wg_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL reg_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL reg_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
   SIGNAL buf_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
@@ -124,66 +118,40 @@ BEGIN
   );
 
   gen_wg : FOR I IN 0 TO g_nof_streams-1 GENERATE
-
-    u_mm_reg : ENTITY work.diag_wg_wideband_reg
-    GENERIC MAP (
-      g_cross_clock_domain => g_cross_clock_domain
-    )
-    PORT MAP (
-      -- Clocks and reset
-      mm_rst      => mm_rst,
-      mm_clk      => mm_clk,
-      st_rst      => st_rst,
-      st_clk      => st_clk,
-    
-      -- Memory Mapped Slave in mm_clk domain
-      sla_in      => reg_mosi_arr(I),
-      sla_out     => reg_miso_arr(I),
-    
-      -- MM registers in st_clk domain
-      st_wg_ctrl  => st_wg_ctrl_arr(I)
-    );
-
-    u_wg_wideband : ENTITY work.diag_wg_wideband
+    u_mms_diag_wg_wideband : ENTITY work.mms_diag_wg_wideband
     GENERIC MAP (
-      g_technology        => g_technology,
-      -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
-      g_buf_dir           => g_buf_dir,
-    
-      -- Wideband parameters
-      g_wideband_factor   => g_wideband_factor,
-    
-      -- Basic WG parameters, see diag_wg.vhd for their meaning
-      g_buf_dat_w         => g_buf_dat_w,
-      g_buf_addr_w        => g_buf_addr_w,
-      g_calc_support      => g_calc_support,
-      g_calc_gain_w       => g_calc_gain_w,
-      g_calc_dat_w        => g_calc_dat_w
+      g_technology         => g_technology,
+      g_cross_clock_domain => g_cross_clock_domain,
+      g_buf_dir            => g_buf_dir,
+      g_wideband_factor    => g_wideband_factor,   
+      g_buf_dat_w          => g_buf_dat_w,
+      g_buf_addr_w         => g_buf_addr_w,
+      g_calc_support       => g_calc_support,
+      g_calc_gain_w        => g_calc_gain_w,
+      g_calc_dat_w         => g_calc_dat_w
     )
     PORT MAP (
-      -- Memory-mapped clock domain
+   -- Memory-mapped clock domain
       mm_rst               => mm_rst,
       mm_clk               => mm_clk,
 
-      mm_wrdata            => buf_mosi_arr(I).wrdata(g_buf_dat_w-1 DOWNTO 0),
-      mm_address           => buf_mosi_arr(I).address(g_buf_addr_w-1 DOWNTO 0),
-      mm_wr                => buf_mosi_arr(I).wr,
-      mm_rd                => buf_mosi_arr(I).rd,
-      mm_rdval             => buf_miso_arr(I).rdval,
-      mm_rddata            => buf_miso_arr(I).rddata(g_buf_dat_w-1 DOWNTO 0),
-
+      reg_mosi             => reg_mosi_arr(I),
+      reg_miso             => reg_miso_arr(I),
+    
+      buf_mosi             => buf_mosi_arr(I),
+      buf_miso             => buf_miso_arr(I),
+    
       -- Streaming clock domain
       st_rst               => st_rst,
       st_clk               => st_clk,
       st_restart           => st_restart,
-    
-      st_ctrl              => st_wg_ctrl_arr(I),
 
       out_ovr              => wg_ovr( (I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ),
       out_dat              => wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w),
       out_val              => wg_val( (I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ),
       out_sync             => wg_sync((I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            )
-    );
+  );
+
 
     -- wire the wg signals to sosi outputs
     -- This is done as per the method used in unb1_bn_capture_input (Apertif)

libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd

@@ -69,10 +69,6 @@ ARCHITECTURE str OF mms_aduh_monitor_arr IS
   SIGNAL buf_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL buf_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
 
-  SIGNAL mon_mean_sum_arr  : t_slv_64_arr(g_nof_streams-1 DOWNTO 0);  -- use fixed 64 bit sum width
-  SIGNAL mon_power_sum_arr : t_slv_64_arr(g_nof_streams-1 DOWNTO 0);  -- use fixed 64 bit sum width
-  SIGNAL mon_sync_arr      : t_sl_arr(g_nof_streams-1 DOWNTO 0);  -- at the mon_sync there are new mean_sum and pwr_sum statistics available
-   
   
 BEGIN
 
@@ -101,55 +97,31 @@ BEGIN
   );
 
   gen_aduh_monitor : FOR I IN 0 TO g_nof_streams-1 GENERATE
-
-    u_mm_reg : ENTITY work.aduh_monitor_reg
-    GENERIC MAP (
-      g_cross_clock_domain => g_cross_clock_domain
-    )
-    PORT MAP (
-      -- Clocks and reset
-      mm_rst            => mm_rst,
-      mm_clk            => mm_clk,
-      st_rst            => st_rst,
-      st_clk            => st_clk,
-    
-      -- Memory Mapped Slave in mm_clk domain
-      sla_in            => reg_mosi_arr(I),
-      sla_out           => reg_miso_arr(I),
-    
-      -- MM registers in st_clk domain
-      st_mon_mean_sum   => mon_mean_sum_arr(I),
-      st_mon_power_sum  => mon_power_sum_arr(I),
-      st_mon_sync       => mon_sync_arr(I)
-    );
-  
-    u_monitor : ENTITY work.aduh_monitor
+    u_mms_aduh_monitor : ENTITY work.mms_aduh_monitor
     GENERIC MAP (
+      g_cross_clock_domain   => g_cross_clock_domain,
       g_symbol_w             => g_symbol_w,
       g_nof_symbols_per_data => g_nof_symbols_per_data,
       g_nof_accumulations    => g_nof_accumulations,
       g_buffer_nof_symbols   => g_buffer_nof_symbols,
       g_buffer_use_sync      => g_buffer_use_sync
-    )
+   )
     PORT MAP (
-      mm_rst         => mm_rst,
-      mm_clk         => mm_clk,
+      -- Clocks and reset
+      mm_rst                 => mm_rst,
+      mm_clk                 => mm_clk,
+      st_rst                 => st_rst,
+      st_clk                 => st_clk,
     
-      buf_mosi       => buf_mosi_arr(I),
-      buf_miso       => buf_miso_arr(I),
+      -- Memory Mapped Slave in mm_clk domain
+      reg_mosi               => reg_mosi_arr(I),
+      reg_miso               => reg_miso_arr(I),
+      buf_mosi               => buf_mosi_arr(I),
+      buf_miso               => buf_miso_arr(I),
     
       -- Streaming inputs
-      st_rst         => st_rst,
-      st_clk         => st_clk,
-    
-      in_sosi        => in_sosi_arr(I),
-    
-      -- Monitor outputs
-      stat_mean_sum  => mon_mean_sum_arr(I),
-      stat_pwr_sum   => mon_power_sum_arr(I),
-      stat_sync      => mon_sync_arr(I)
+      in_sosi                => in_sosi_arr(I)
     );
-
   END GENERATE;
   
 END str;