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Commit 9d97ca4a authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added FIFO and deinterleaver.

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applications/arts/designs/arts_unb1_sc1_3dish_1pol/src/vhdl/arts_unb1_sc1_3dish_1pol.vhd
+ 95
− 17
View file @ 9d97ca4a
......@@ -95,8 +95,10 @@ ARCHITECTURE str OF arts_unb1_sc1_3dish_1pol IS
-------------------------------------------------------------------------------
-- ARTS SC1
-------------------------------------------------------------------------------
CONSTANT c_channel_compl_dat_w : NATURAL := 8;
CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w;
CONSTANT c_channel_compl_dat_w : NATURAL := 8;
CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w;
CONSTANT c_nof_apertif_bf_units : NATURAL := 4; -- 4 bf_units per Apertif FN
CONSTANT c_nof_beamlets : NATURAL := 88; --88 beamlets per node, 704 in total
-------------------------------------------------------------------------------
-- 10GbE input stage
......@@ -150,17 +152,21 @@ ARCHITECTURE str OF arts_unb1_sc1_3dish_1pol IS
SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- DP split, Repack
-- Beamlet selection
-------------------------------------------------------------------------------
CONSTANT c_nof_sc1_symbols : NATURAL := 24;
CONSTANT c_nof_sc1_symbols : NATURAL := 24;
SIGNAL dp_split_src_in_2arr_2 : t_dp_siso_2arr_2(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_split_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_split_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_split_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_deinterleave_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_deinterleave_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_repack_data_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_repack_data_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_split_src_in_2arr_2 : t_dp_siso_2arr_2(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_split_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_split_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
SIGNAL dp_split_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- BF Unit
......@@ -448,24 +454,96 @@ BEGIN
src_out_arr => dp_bsn_align_src_out_arr
);
gen_bsn_align_src_in_arr: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
dp_bsn_align_src_in_arr(i) <= c_dp_siso_rdy;
END GENERATE;
-------------------------------------------------------------------------------
-- Extract the 4 bf_unit substreams from each 10GbE input stream
-- . 3 64b streams -> 3*4 16b streams
-- . Incoming beamlets (same for each of the 3 10GbE inputs): 3 inputs*704 beamlets/FPGA
-- . 10GbE 64b word index ) [0],[1], ..[175]
-- . BF Stream 0 ) 0, 1 , .. 175 (Selected)
-- . BF Stream 1 ) 256,257 , .. 431 (discarded)
-- . BF Stream 2 ) 512,513 , .. 687 (discarded)
-- . BF Stream 3 ) 768,769 , .. 943 (discarded)
-------------------------------------------------------------------------------
gen_dp_stream_deconcat : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
dp_deinterleave_snk_in_arr(i) <= func_dp_stream_deconcat(dp_bsn_align_src_out_arr(i), c_nof_apertif_bf_units, c_channel_dat_w)(0); --Only use bf_unit stream 0
END GENERATE;
-------------------------------------------------------------------------------
-- Deinterleave 3 streams into 3*2 streams
-------------------------------------------------------------------------------
gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
u_deinterleave : ENTITY dp_lib.dp_deinterleave
GENERIC MAP (
g_nof_out => 2,
g_block_size_int => 1,
g_block_size_output => c_nof_beamlets,
g_dat_w => c_channel_dat_w,
g_use_ctrl => TRUE,
g_use_sync_bsn => TRUE,
g_align_out => TRUE,
g_use_complex => FALSE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => dp_deinterleave_snk_in_arr(i),
src_out_arr => dp_deinterleave_src_out_2arr_2(i)
);
END GENERATE;
-------------------------------------------------------------------------------
-- Rewire 3*2 streams into 3 streams (discard odd beamlets)
-------------------------------------------------------------------------------
gen_rewire : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
dp_deinterleave_src_out_arr(i) <= dp_deinterleave_src_out_2arr_2(i)(0); -- Beamlet 0, 2, 4, .. 174
-- dp_deinterleave_src_out_2arr_2(i)(1); -- Beamlet 1, 3, 5, .. 175
END GENERATE;
-------------------------------------------------------------------------------
-- bf_unit needs flow control
-------------------------------------------------------------------------------
gen_dp_fifo_sc: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP(
g_data_w => c_channel_dat_w,
g_bsn_w => 64,
g_fifo_size => 30,
g_use_bsn => TRUE,
g_use_sync => TRUE,
g_use_ctrl => TRUE
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => dp_deinterleave_src_out_arr(i),
src_in => dp_fifo_sc_src_in_arr(i),
src_out => dp_fifo_sc_src_out_arr(i)
);
END GENERATE;
-------------------------------------------------------------------------------
-- Forward only the first 24 64b words
-- . This will forward 4 sets (bf_units) of 24 beamlets. We'll discard
-- substreams 1..3 later and only use substream 0 (beamlets 0..23).
-- Forward only the first 24 beamlets: 0,2,4, .. 46.
-------------------------------------------------------------------------------
gen_dp_split: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
u_dp_split : ENTITY dp_lib.dp_split
GENERIC MAP (
g_data_w => c_xgmii_data_w,
g_symbol_w => c_xgmii_data_w,
g_data_w => c_channel_dat_w,
g_symbol_w => c_channel_dat_w,
g_nof_symbols => c_nof_sc1_symbols
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_out => dp_bsn_align_src_in_arr(i),
snk_in => dp_bsn_align_src_out_arr(i),
snk_in => dp_fifo_sc_src_out_arr(i),
snk_out => dp_fifo_sc_src_in_arr(i),
src_in_arr => dp_split_src_in_2arr_2(i),
src_out_arr => dp_split_src_out_2arr_2(i)
......
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