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Commit 7e6ba537 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Defaulted all MISO buses to c_mem_miso_rst.

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applications/arts/designs/arts_unb1_sc1_3dish_1pol/src/vhdl/arts_unb1_sc1_3dish_1pol_mm_master.vhd
+ 25
− 25
View file @ 7e6ba537
......@@ -52,26 +52,26 @@ ENTITY arts_unb1_sc1_3dish_1pol_mm_master IS
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_irq : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso;
reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso;
reg_epcs_mosi : OUT t_mem_mosi;
reg_epcs_miso : IN t_mem_miso;
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso;
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
pio_system_info_mosi : OUT t_mem_mosi;
pio_system_info_miso : IN t_mem_miso;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
eth1g_tse_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
eth1g_reg_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
eth1g_ram_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
reg_unb_sens_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
reg_epcs_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_epcs_miso : IN t_mem_miso := c_mem_miso_rst;
reg_remu_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_remu_miso : IN t_mem_miso := c_mem_miso_rst;
reg_ppsh_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
pio_system_info_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
pio_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
rom_unb_system_info_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
reg_wdi_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
reg_mdio_0_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_mdio_0_miso : IN t_mem_miso := c_mem_miso_rst;
reg_mdio_1_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
......@@ -87,13 +87,13 @@ ENTITY arts_unb1_sc1_3dish_1pol_mm_master IS
reg_tr_xaui_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
ram_bf_unit_ss_ss_wide_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_bf_unit_ss_ss_wide_miso : IN t_mem_miso;
ram_bf_unit_ss_ss_wide_miso : IN t_mem_miso := c_mem_miso_rst;
ram_bf_unit_bf_weights_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_bf_unit_bf_weights_miso : IN t_mem_miso;
ram_bf_unit_bf_weights_miso : IN t_mem_miso := c_mem_miso_rst;
ram_bf_unit_st_sst_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_bf_unit_st_sst_miso : IN t_mem_miso;
ram_bf_unit_st_sst_miso : IN t_mem_miso := c_mem_miso_rst;
reg_bf_unit_st_sst_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_bf_unit_st_sst_miso : IN t_mem_miso;
reg_bf_unit_st_sst_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_xonoff_output_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_dp_xonoff_output_miso : IN t_mem_miso
);
......@@ -108,7 +108,7 @@ ARCHITECTURE str OF arts_unb1_sc1_3dish_1pol_mm_master IS
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC ;
SIGNAL sim_eth_psc_access : STD_LOGIC ;
SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_eth1g_reg_miso : t_mem_miso;
SIGNAL i_eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL mm_rst_n : STD_LOGIC ;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
......
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