Skip to content
Snippets Groups Projects
Commit 9c51badc authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Merge branch 'master' of git.astron.nl:desp/hdl

parents b42b534b efadbff8
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
Showing
with 83 additions and 32 deletions
boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+ 0
− 2
View file @ 9c51badc
......@@ -26,7 +26,6 @@ regression_test_vhdl =
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
......@@ -35,7 +34,6 @@ quartus_copy_files =
quartus/sopc_unb1_bn_capture.sopc .
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+ 0
− 3
View file @ 9c51badc
......@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/base/diag/src/data data
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
......@@ -26,7 +24,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_bn_terminal_bg.sopc .
$RADIOHDL_WORK/libraries/base/diag/src/data data
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_ddr3/doc/README
+ 1
− 1
View file @ 9c51badc
......@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
......
boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+ 0
− 3
View file @ 9c51badc
......@@ -17,18 +17,15 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_ddr3.sopc .
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -160,7 +160,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+ 1
− 1
View file @ 9c51badc
......@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
......
boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -167,7 +167,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+ 0
− 2
View file @ 9c51badc
......@@ -17,7 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
......@@ -28,7 +27,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb_ddr3_transpose.sopc .
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -133,7 +133,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+ 0
− 3
View file @ 9c51badc
......@@ -16,15 +16,12 @@ test_bench_files =
[modelsim_project_file]
#modelsim_copy_files = src/hex hex
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_fn_terminal_db.sopc .
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -146,7 +146,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_heater/doc/README
+ 1
− 1
View file @ 9c51badc
......@@ -16,7 +16,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
......
boards/uniboard1/designs/unb1_heater/hdllib.cfg
+ 0
− 3
View file @ 9c51badc
......@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
......@@ -24,7 +22,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_heater.qsys .
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -122,7 +122,7 @@ BEGIN
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_minimal/doc/README
+ 1
− 1
View file @ 9c51badc
......@@ -18,7 +18,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
rm $UNB/Software/python/sim/* # (optional)
rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
......
boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+ 0
− 2
View file @ 9c51badc
......@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
BEGIN
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml 0 → 100644
+ 72
− 0
View file @ 9c51badc
schema_name : args
schema_version: 1.0
schema_type : fpga
hdl_library_name: unb1_minimal_sopc
fpga_name : unb1_minimal_sopc
fpga_description: |
"unb1_minimal system for sopc"
peripherals:
- peripheral_name: rom_system_info
subsystem_name : ''
slave_port_names:
- rom_system_info
parameters:
- { name: lock_base_address, value: 0x1000 }
- peripheral_name: reg_system_info
subsystem_name : ''
slave_port_names:
- pio_system_info
parameters:
- { name: lock_base_address, value: 0x0 }
- peripheral_name: ctrl_unb1_board
subsystem_name : ''
slave_port_names:
- pio_wdi
- peripheral_name: unb1_board_wdi_reg
subsystem_name : ''
slave_port_names:
- reg_wdi
- peripheral_name: eth1g
subsystem_name : ''
slave_port_names:
- avs_eth_0_mms_tse
- avs_eth_0_mms_reg
- avs_eth_0_mms_ram
- peripheral_name: ppsh
subsystem_name : ''
slave_port_names:
- pio_pps
- peripheral_name: epcs_reg
subsystem_name : ''
slave_port_names:
- reg_epcs
- reg_mmdp_ctrl
- reg_mmdp_data
- reg_dpmm_ctrl
- reg_dpmm_data
parameters:
- { name : g_sim_flash_model, value: FALSE }
- peripheral_name: remu_reg
subsystem_name : ''
slave_port_names:
- reg_remu
- peripheral_name: unb1_board_sens_reg
subsystem_name : ''
slave_port_names:
- reg_unb_sens
parameters:
- { name : g_sim, value: FALSE }
- { name : g_clk_freq, value: 125E6 }
- { name : g_temp_high, value: 85 }
boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+ 1
− 1
View file @ 9c51badc
......@@ -151,7 +151,7 @@ BEGIN
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
......
boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+ 0
− 3
View file @ 9c51badc
......@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
src/hex hex
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
......@@ -27,7 +25,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex
$RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment