diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 159cc2b5ed8f7b630c5909477ffcd0e91ca783e4..2c87641ca55b5a52ce9c4437f4849274ac674de3 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -26,7 +26,6 @@ regression_test_vhdl =
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
@@ -35,7 +34,6 @@ quartus_copy_files =
quartus/sopc_unb1_bn_capture.sopc .
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index cd32b3ec5e81964ef2a3d9e3e701170608ad756d..9368e22ad325e4676b993d61512b0b9fd1f7b785 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
@@ -26,7 +24,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_bn_terminal_bg.sopc .
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index 4134e5df3170b97aa95b4ef5b8a1f7e3d89180b9..dcc27dd23312d4c54bb469591cb58ecfe5482341 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 8cfde04c82aa49fb2701012f596429de1ada0b5f..89321855be5b9591595b7b3c57d742d82ba8f64f 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -17,18 +17,15 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_ddr3.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 7a27dbfa212ce9fc6f38a7f1463d59354c6b4862..9c2a5cefd3b87cb296d0673e1fc9fadfcc48f7de 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -160,7 +160,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index 489688ec457794329f95d5d2c59c6efadd7f370e..43dcd7791d203a5c3e68da9950f995b562b16edd 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index b22bc96ef6876c494d0f5959118f569732f3daaf..18f4514907bed8b19a2151ae7eb6f4e3153338a1 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -167,7 +167,7 @@ BEGIN
cal_clk <= i_cal_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 23d49faca31ece9b8e32a2bf93ee0e4e621d1bb6..3deda821337e0d7909ffb96b8dc5c75c6f716e43 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -17,7 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -28,7 +27,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb_ddr3_transpose.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 1bbf679a9b2be2030f0f4d4d3f20ccfb801d3259..3d5bd6df8e1330930a40abedada557b2f4b20ac7 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -133,7 +133,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index bb2137004fb411473abe12b4106ce889016e5607..908c0f97085a4bdaa5d9fb02a1ce8d20162e681d 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -16,15 +16,12 @@ test_bench_files =
[modelsim_project_file]
#modelsim_copy_files = src/hex hex
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_fn_terminal_db.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 48b37524cc93f255f3a4479aba797b50df15aabc..3799af2d9301feaf9798d11f3bcfed6435accb82 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -146,7 +146,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index a907cf2b91ffcb459d93f9ef3954d44bc0757e43..4b3e99c67cbd5fb485cd35f6b531738da64745e5 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -16,7 +16,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 2e8fbc26e47c66ec476e9c63b1e6fafe06df3b9f..3124faa9b5ec78cd53c1007ea48847f895d0d4ee 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
@@ -24,7 +22,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_heater.qsys .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index bb47b661ed4d6abbaa0974821036d3669adc6479..adbd2679ab8321b3672e88ce7129ce5f5d22e343 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -122,7 +122,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index d85df74cd153f712b2dcd7dabac0ac6106ced633..a0085f2f59c52ce8eb99e1dec7658b1c7d4b395d 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -18,7 +18,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 4d82a8de6e274515ac47014aeaed757ae303a309..f78ab28d3cb8808fe0e41c5887748c3b6deec7ab 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 96883ccde9b40f852b8bd541ccd5948b839cc74c..61a2baef4a5b7cf427a59a245158178c2be433d8 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -122,7 +122,7 @@ ARCHITECTURE str OF mmm_unb1_minimal_qsys_wo_pll IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d6ee3b63770c2411d856bd2c111f507784a6a7e5
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.fpga.yaml
@@ -0,0 +1,72 @@
+schema_name : args
+schema_version: 1.0
+schema_type : fpga
+
+hdl_library_name: unb1_minimal_sopc
+
+fpga_name : unb1_minimal_sopc
+fpga_description: |
+ "unb1_minimal system for sopc"
+
+peripherals:
+ - peripheral_name: rom_system_info
+ subsystem_name : ''
+ slave_port_names:
+ - rom_system_info
+ parameters:
+ - { name: lock_base_address, value: 0x1000 }
+
+ - peripheral_name: reg_system_info
+
+ subsystem_name : ''
+ slave_port_names:
+ - pio_system_info
+ parameters:
+ - { name: lock_base_address, value: 0x0 }
+
+ - peripheral_name: ctrl_unb1_board
+ subsystem_name : ''
+ slave_port_names:
+ - pio_wdi
+
+ - peripheral_name: unb1_board_wdi_reg
+ subsystem_name : ''
+ slave_port_names:
+ - reg_wdi
+
+ - peripheral_name: eth1g
+ subsystem_name : ''
+ slave_port_names:
+ - avs_eth_0_mms_tse
+ - avs_eth_0_mms_reg
+ - avs_eth_0_mms_ram
+
+ - peripheral_name: ppsh
+ subsystem_name : ''
+ slave_port_names:
+ - pio_pps
+
+ - peripheral_name: epcs_reg
+ subsystem_name : ''
+ slave_port_names:
+ - reg_epcs
+ - reg_mmdp_ctrl
+ - reg_mmdp_data
+ - reg_dpmm_ctrl
+ - reg_dpmm_data
+ parameters:
+ - { name : g_sim_flash_model, value: FALSE }
+
+ - peripheral_name: remu_reg
+ subsystem_name : ''
+ slave_port_names:
+ - reg_remu
+
+ - peripheral_name: unb1_board_sens_reg
+ subsystem_name : ''
+ slave_port_names:
+ - reg_unb_sens
+ parameters:
+ - { name : g_sim, value: FALSE }
+ - { name : g_clk_freq, value: 125E6 }
+ - { name : g_temp_high, value: 85 }
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index 2c0fee9797b0edc7eb88bc91077cced153f16be9..a518c6b0cbd334a271934ee19123ba6d4b181a98 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -151,7 +151,7 @@ BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index e56f106393f30eaebd6b2caf8797854ea5be96c4..f7db8733bd9c89611f906dfd740d56ecf1524ef2 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
src/hex hex
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
@@ -27,7 +25,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index bd3dee21cce9a4163932f7d00ec78c4ab3d1cadd..52d2499977120295d334bfc915bb7e30abb4f392 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -268,7 +268,7 @@ ARCHITECTURE str OF mmm_unb1_terminal_bg_mesh_db IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 9eca9c326ae3ef0a160f23e4234264c9c77ca751..e2fdce714481f03d9ec2e3d12e35af559ed25dd8 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -46,7 +46,7 @@ The following revisions are available for unb1_test (see the directories in ../r
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb1
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index d84c1f1b2137f50ce0e0b86ad8fc97357163cd70..65ddbb4c7cb5c30cb8f9847d9d15b4ee594fac00 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7fd9b5198b0b5bae433650aa53e8b847c17365a8..e8c27dfe23e1306903e4a5123f234abdec492ac7 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,7 +257,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index f1eecf8d27bb9bcd935d29a680d97f070b765ead..5e10bf15e3c51ad17bf3c4ebfd9ca25b5ae84c84 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -15,7 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
# src/hex hex
@@ -25,7 +24,6 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus/qsys_unb1_tr_10GbE.qsys .
# src/hex/ hex
diff --git a/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..1dc9ae0ba5d39c6614431d04a5b0a2bbab1ebd83
--- /dev/null
+++ b/boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml
@@ -0,0 +1,182 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : unb1_board
+hdl_library_description: " This is the description for the unb1_board package "
+
+peripherals:
+ -
+ peripheral_name: rom_system_info
+ slave_ports:
+ -
+ # rom_system_info
+ slave_prefix : WORK
+ slave_name : ROM_SYSTEM_INFO
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : field_rom_info
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 1024
+ field_description: |
+ "address place for rom_system_info"
+ slave_description: " rom_info "
+
+ peripheral_description: |
+ " settings for rom_system_info register "
+ -
+ peripheral_name: reg_system_info
+ slave_ports:
+ -
+ # reg_system_info
+ slave_prefix : WORK
+ slave_name : REG_SYSTEM_INFO
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : field_reg_info
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 31
+ field_description: |
+ "address place for reg_system_info"
+ slave_description: " reg_info "
+
+ peripheral_description: |
+ " settings for reg_system_info register "
+
+ # peripheral, unb1_board_wdi_reg
+ -
+ peripheral_name: ctrl_unb1_board
+
+ slave_ports:
+ -
+ # actual hdl name: unb1_board_wdi_reg
+ slave_prefix : UNB1_BOARD
+ slave_name : PIO_WDI
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : nios_reset
+ access_mode : WO
+ address_offset : 0x0
+ number_of_fields: 4
+ field_description: " Reset done by nios "
+
+ slave_description: "Reset register, for nios "
+
+ peripheral_description: " "
+
+ # peripheral, unb1_board_wdi_reg
+ -
+ peripheral_name: unb1_board_wdi_reg
+
+ slave_ports:
+ -
+ # actual hdl name: unb1_board_wdi_reg
+ slave_prefix : UNB1_BOARD
+ slave_name : WDI
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : reset_word
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
+
+ slave_description: "Reset register, if the right value is provided the factory image will be reloaded "
+
+ peripheral_description: " "
+
+ # periheral, unb1_board_sens
+ -
+ peripheral_name: unb1_board_sens_reg
+
+ parameters:
+ - { name: g_sim, value: FALSE }
+ - { name: g_clk_freq, value: c_unb1_board_mm_clk_freq_125M }
+ - { name: g_temp_high, value: 85 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_unb1_sens
+ slave_prefix : UNB1_BOARD
+ slave_name : SENS
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : sens_data
+ width : 8
+ access_mode : RO
+ address_offset: 0x0
+ number_of_fields: 4
+ field_description: |
+ " data array with sens data
+ 0x0 = fpga temperature in degrees (two's complement)
+ 0x1 = eth_temp temperature in degrees (two's complement)
+ 0x2 = hot_swap_v_sens
+ 0x3 = hot_swap_v_source"
+
+ -
+ field_name : sens_err
+ width : 1
+ access_mode : RO
+ address_offset: 0x4
+ radix : unsigned
+ field_description: ""
+
+ -
+ field_name : temp_high
+ width : 7
+ address_offset: 0x5
+ reset_value : g_temp_high
+ software_value: g_temp_high
+ field_description: ""
+
+ slave_description: " "
+
+ peripheral_description: |
+ "
+ +-----------------------------------------------------------------------------+
+ |31 (byte3) 24|23 (byte2) 16|15 (byte1) 8|7 (byte0) 0| wi |
+ |-----------------------------------------------------------------------|-----|
+ | xxx fpga_temp = sens_data[0][7:0]| 0 |
+ |-----------------------------------------------------------------------|-----|
+ | xxx eth_temp = sens_data[1][7:0]| 1 |
+ |-----------------------------------------------------------------------|-----|
+ | xxx hot_swap_v_sense = sens_data[2][7:0]| 2 |
+ |-----------------------------------------------------------------------|-----|
+ | xxx hot_swap_v_source = sens_data[3][7:0]| 3 |
+ |-----------------------------------------------------------------------|-----|
+ | xxx sens_err[0]| 4 |
+ |-----------------------------------------------------------------------|-----|
+ | xxx temp_high[6:0]| 5 |
+ +-----------------------------------------------------------------------------+
+ * The fpga_temp and eth_temp are in degrees (two's complement)
+ * The hot swap voltages depend on:
+ . From i2c_dev_ltc4260_pkg:
+ LTC4260_V_UNIT_SENSE = 0.0003 -- 0.3 mV over Rs for current sense
+ LTC4260_V_UNIT_SOURCE = 0.4 -- 400 mV supply voltage (e.g +48 V)
+ LTC4260_V_UNIT_ADIN = 0.01 -- 10 mV ADC
+
+ . From UniBoard unb_sensors.h:
+ SENS_HOT_SWAP_R_SENSE = 0.005 -- R sense on UniBoard is 5 mOhm (~= 10 mOhm // 10 mOhm)
+ SENS_HOT_SWAP_I_UNIT_SENSE = LTC4260_V_UNIT_SENSE / SENS_HOT_SWAP_R_SENSE
+ SENS_HOT_SWAP_V_UNIT_SOURCE = LTC4260_V_UNIT_SOURCE
+
+ ==>
+ Via all FN and BN:
+ 0 = FPGA temperature = TInt8(fpga_temp)
+ Only via BN3:
+ 1 = UniBoard ETH PHY temperature = TInt8(eth_temp)
+ 2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
+ 3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
+ 4 = I2C error status for BN3 sensors access only, 0 = ok"
+
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index d4c4b3ef19935eaddc50b6dd1d38bcd328db7e9c..037b0a8df8170885130d85039477ac353bf44fa8 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2
# in Modelsim do:
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index db4628496d5407dcebe64cc739e0371b8220c88e..2c1f0c7f90cc18aef2845c7461d3e5de4ae4e27b 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 5c311198c8fb13862603499e0706edad56f58ab6..0dff5ebf0ab9bcd3cd838ef7ffe626ee466cf51d 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -54,7 +54,7 @@ The following revisions are available for unb2_test (see the directories in ../r
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index a9226f63e6109e91ed3663c7f3b489139345f023..38dd414bf32dceb289966d3dd9f6c503f7b43fca 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -284,7 +284,7 @@ ARCHITECTURE str OF mmm_unb2_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 45d88bd21b9f2bd7d296df1929051fe45efe5a7b..8788e379fa87b9245e747a06d0a90b8250953e68 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2a
# in Modelsim do:
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 7d97a930169989f621da500a586be25d11782034..6870c7a570c70a47bf8b19a8a513fe91460e4baf 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2a_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 552ed433c518889dfce99210f34f3a5f342229e3..37859f9f848528b736ddcff61a7073495f38679f 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2a
# in Modelsim do:
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 338878470393169081645cc7eb20659a0bc95803..a7548b0735eb816d2ecf80840555ed2f1604525e 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2a_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index 4d8244dfcf3ee35e771167de7beabdd10aa47134..ce1710cbd2aebe9cd61b66a764df3f084920776f 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2a_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2a
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 7f07f1f7f3ed4e55110b774aa62bbd87d13794b1..06f8aeedc793134557ebebb2f146f11ddb8529f7 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2a_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index 4958c61efd971a89c4784bcd8119226a5cfefe28..b2f7defb7b919f496224df583014d5a518879179 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 01014dc0fc3dc13e4f0f05f6dbe55a326a10deb2..cad8b1c16ab141d979202f288102f8b79ebb9e16 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -15,14 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index 782748e7d4e2e3d4b6e5ec42794552666401f6cb..98475ca46038674446a0ad90053a8cacfab96856 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2b_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_jesd/doc/README b/boards/uniboard2b/designs/unb2b_jesd/doc/README
index a8ee798172b26c69d51affd65034e1d8b8b5b3c6..4548387ac8254d2f9023e2483e7eb9900fbcc469 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/doc/README
+++ b/boards/uniboard2b/designs/unb2b_jesd/doc/README
@@ -37,7 +37,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index 534dac3205b85021a62dcc84a3525f5dc9928a79..dc01f1470182e33f393473bf917dc96820c9928c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -15,14 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index 1c12d1247f00e6840156da2dc3302355e46a0ba1..eb5cae66ce7da505c28e903530687f401ab34072 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 2fdf2728e16d86411d5f017b63c36f9e3a65406e..c14007d56250625c914f10559a915a752fbea450 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -15,13 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index c482ecfc35216fce386e1b046dbe31d06d33f429..9c99f381a3f76fc1e91acafddabb8b3b63e9fede 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2b_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 7dbf81984351624dd2eafbc0701c3b960c403318..31575a05f4f73a2f8f1fbb071b9fc92b8054415e 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2b_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2b
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2b/designs/unb2b_test/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
index 3745d759255a82e6a87a6bd55dc63f7a851e54fe..e22cda32474b5f54b09826ac4b58e4695ea42eb3 100644
--- a/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 301f25db6d31f29d02654c220272a3cdbbaeeea8..842561e71fc06414b7f1c7a7bdb8fadccd5cb7a6 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2b_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_heater/doc/README.txt b/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
index 79694e18e8133fcc8720b7266b90967286687efe..58454429a6fb3899c28619ce2ff5e4b6c1b13e2e 100644
--- a/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
index d4412328b9681a9925e206877d1dcbdf88e3a942..385dbb59a6925d92e91c658378d1c501adf4af57 100644
--- a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
@@ -15,21 +15,18 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_heater_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl b/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
index e99fb59c459dab329d3d13cc82d2b46497f8231a..236269c156df5a03803144b912fb41eedabfade7 100644
--- a/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
@@ -18,4 +18,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
index f405ed1f61cd85877eade8cc87693d49cb77a479..6fb087f03365456d8022c8f12ee1253b15831733 100644
--- a/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_heater/src/vhdl/mmm_unb2c_heater.vhd
@@ -115,7 +115,7 @@ ARCHITECTURE str OF mmm_unb2c_heater IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_jesd/doc/README b/boards/uniboard2c/designs/unb2c_jesd/doc/README
index 6c27ae37d1e5161f83ccff1c89d829ecd56971ef..f25a57e1550817bf0d7fd6549f02c3b6af4312f6 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/doc/README
+++ b/boards/uniboard2c/designs/unb2c_jesd/doc/README
@@ -37,7 +37,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
index 6de0ac38e2c41d76dfa95534a219dbab6734dc5e..74dd04a7b4c72bce1921dac14bf648ecf7da05e4 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
@@ -15,18 +15,16 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd.sdc
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
index 11abd8a9c0b224f7a08d2cf01fb2c50c53612f5d..e580c1600a3dc583d8c5cebea32f2a9b3dfe9c2b 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
@@ -20,7 +20,7 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd_node0.sdc
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
index 7d946e583e2561ce47c505309cb56bc020eb9326..7a59e62d82807f96856aeb647449f417d9ade20e 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
@@ -20,7 +20,7 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd_node3.sdc
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README b/boards/uniboard2c/designs/unb2c_minimal/doc/README
index 5e13e9cf030fc7ace33c3d97892b82849545d600..10c3150b6c5dcb5f8c9f140af40f867a896ed11d 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/doc/README
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index c6024ae9717836ca600b940fe0f128cdea3ee151..56e214f2466ed59c77fd93296955e7e8b0818829 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -15,20 +15,18 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
index 121b2146078a8a40e0687b404a7a53232f48fcb9..ae417258f888c910d593c6ab6e5117615ebbd36f 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index 149159392034a6d9dbfdba12ac063c5ac2ebca65..4f3f7b17ee743180825b03b5f5ef177e4f654b5a 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -111,7 +111,7 @@ ARCHITECTURE str OF mmm_unb2c_minimal IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/boards/uniboard2c/designs/unb2c_test/doc/README.txt b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
index 10f984b71e861cfca34a2950fbb8cab09659fcce..bf6717f0455a3a0f4c15852c188afc86dcafa6d1 100644
--- a/boards/uniboard2c/designs/unb2c_test/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2c_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm -r ${HDL_IOFILE_SIM_DIR}/* # (optional)
run_modelsim unb2c
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
index c98b1f0172f93e8cbd8a1caf5b7f13e68c12f6b3..cff24fd96bd74e5c838947956eb17fee22aeaa33 100644
--- a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl b/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
index 0bc636cbf0a4008e2948d0cd86c926662df19e82..de0a720193bdd4f5abd6984cd3375a3409741151 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 94d56cf841676a500fd685cc41325faf682236c2..de860d3ffb575f7eb18cc911a9c506739e8da20b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_10GbE_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 6c752d86c0e20fa1f7d3b925c845bb6e85ae5d01..e175ad064068c0b2f7c1591ed2135389278d418e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -287,7 +287,7 @@ ARCHITECTURE str OF mmm_unb2c_test IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/init_hdl.sh b/init_hdl.sh
index fd1a853c1e81daa421d7f33776dd7f634b9e142c..42eeaaab84b5baf6d436e9612c7e9033a8fe730e 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -41,6 +41,13 @@ export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
export HDL_BUILD_DIR=${HDL_BUILD_DIR:-${RADIOHDL_WORK}/build}
echo "HDL environment will be setup for" $RADIOHDL_WORK
+# modelsim uses this sim dir for testing
+export HDL_IOFILE_SIM_DIR=${HDL_IOFILE_SIM_DIR:-${HDL_BUILD_DIR}/sim}
+if ! [[ -e HDL_IOFILE_SIM_DIR ]]; then
+ echo "make sim dir"
+ mkdir ${HDL_BUILD_DIR}/sim
+fi
+rm -r ${HDL_BUILD_DIR}/sim/*
# copy git user_componets.ipx into Altera dir's
for altera_dir in ${ALTERA_DIR}/*; do
@@ -50,7 +57,6 @@ for altera_dir in ${ALTERA_DIR}/*; do
fi
done
-
if [ -z "${RADIOHDL_GEAR}" ]; then
. ../radiohdl/init_radiohdl.sh
fi
diff --git a/libraries/base/diag/diag.peripheral.yaml b/libraries/base/diag/diag.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..65d1b28189256ecc88e25db0154d238a8e09225d
--- /dev/null
+++ b/libraries/base/diag/diag.peripheral.yaml
@@ -0,0 +1,258 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : diag
+hdl_library_description: " This is the description for the bf package "
+
+peripherals:
+ -
+ peripheral_name: diag_block_gen
+
+ parameters:
+ - { name: g_nof_streams, value: 1 }
+ - { name: g_buf_dat_w , value: 32 }
+ - { name: g_buf_addr_w , value: 7 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_diag_bg
+ slave_prefix : DIAG
+ slave_name : BG
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : Enable
+ width : 2
+ address_offset: 0x0
+ field_description: |
+ "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
+ -
+ field_name : Samples_per_packet
+ width : 16
+ address_offset: 0x1
+ reset_value : 256
+ field_description: |
+ "This REG specifies the number samples in a packet"
+ -
+ field_name : Blocks_per_sync
+ width : 16
+ address_offset: 0x2
+ reset_value : 781250
+ field_description: |
+ "This REG specifies the number of packets in a sync period"
+ -
+ field_name : Gapsize
+ width : 16
+ address_offset: 0x3
+ reset_value : 80
+ field_description: |
+ "This REG specifies the gap in number of clock cycles between two consecutive packets"
+ -
+ field_name : Mem_low_address
+ width : 8
+ address_offset: 0x4
+ field_description: |
+ "This REG specifies the starting address for reading from the waveform memory"
+ -
+ field_name : Mem_high_address
+ width : 8
+ address_offset: 0x5
+ field_description: |
+ "This REG specifies the last address to be read when from the waveform memory"
+ -
+ field_name : BSN_init_low
+ address_offset: 0x6
+ field_description: |
+ "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
+ -
+ field_name : BSN_init_high
+ address_offset: 0x7
+ field_description: |
+ "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
+ -
+ # actual hdl name: ram_diag_bg
+ slave_prefix : DIAG
+ slave_name : BG
+ slave_postfix: RAM
+ number_of_slaves: g_nof_streams
+ slave_type : RAM
+ fields:
+ -
+ field_name: diag_bg
+ width: g_buf_dat_w
+ number_of_fields: 2**g_buf_addr_w
+ field_description : |
+ "Contains the Waveform data for the data-streams to be send"
+ peripheral_description: |
+ "Block generator"
+ -
+ peripheral_name: diag_data_buffer
+
+ parameters:
+ - { name: g_nof_streams , value: 1 }
+ - { name: g_data_w , value: 32 }
+ - { name: g_buf_nof_data, value: 1024 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_diag_data_buffer
+ slave_prefix : DIAG
+ slave_name : DATA_BUFFER
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : Sync_cnt
+ access_mode : RO
+ address_offset: 0x0
+ field_description: |
+ "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
+ (cleared when the last data word from the buffer is read)"
+ -
+ field_name : Word_cnt
+ access_mode : RO
+ address_offset: 0x1
+ field_description: |
+ "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
+ -
+ field_name : Valid_cnt_arm_ena
+ address_offset: 0x2
+ field_description: |
+ "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
+ Arm_enable: Write to this REG to arm the system.
+ After the system is armed the next syn pulse will trigger the acquisition of data."
+ -
+ field_name : Reg_sync_delay
+ address_offset: 0x3
+ field_description: |
+ "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
+ before the data is written to the databuffer."
+ -
+ field_name : Version
+ access_mode : RO
+ address_offset: 0x7
+ field_description: |
+ "Version contains the version number of the databuffer peripheral."
+ slave_description: ""
+ -
+ # actual hdl name: ram_diag_data_buffer
+ slave_prefix : DIAG
+ slave_name : DATA_BUFFER
+ slave_postfix: RAM
+ number_of_slaves: g_nof_streams
+ slave_type : RAM
+ fields:
+ -
+ field_name : ram
+ width : g_data_w
+ number_of_fields: g_buf_nof_data
+ field_description: |
+ "Contains the data that is being captured."
+ slave_description: ""
+
+ peripheral_description: |
+ "Peripheral diag_data_buffer
+
+ Memory map RAM_DIAG_DATA_BUFFER
+
+ If there is only one instance then the RAM name is RAM_DIAG_DATA_BUFFER, else it
+ gets an instanceName as post fix so RAM_DIAG_DATA_BUFFER_<instanceName|.
+
+ The diag_data_buffer can store multiple streams in parallel. For example
+ 1024 data words for 16 streams the memory map becomes: 16
+
+
+ streamNr = 0:
+ +------------------------------------------------------------+
+ | byte 3 | byte 2 | byte 1 | byte 0 | wi |
+ |------------------------------------------------------------|
+ | data_0[31:0] | 0 |
+ | data_1[31:0] | 1 |
+ | ... | .. |
+ | data_1023[31:0] | 1023 |
+ +------------------------------------------------------------+
+
+
+ streamNr = 1:
+ +------------------------------------------------------------+
+ | byte 3 | byte 2 | byte 1 | byte 0 | wi |
+ |------------------------------------------------------------|
+ | data_0[31:0] | 1024 |
+ | data_1[31:0] | 1025 |
+ | ... | .. |
+ | data_1023[31:0] | 2047 |
+ +------------------------------------------------------------+
+
+
+ streamNr = 15:
+ +------------------------------------------------------------+
+ | byte 3 | byte 2 | byte 1 | byte 0 | wi |
+ |------------------------------------------------------------|
+ | data_0[31:0] | 15360 |
+ | data_1[31:0] | 15361 |
+ | ... | .. |
+ | data_1023[31:0] | 16383 |
+ +------------------------------------------------------------+
+
+
+ Remarks:
+ - The data buffer stores valid data samples until it is full.
+ - The data buffer fills again after an external sync pulse or after the
+ last data word was read via the MM bus, dependend on whether the generic
+ g_use_in_sync is TRUE or FALSE in diag_data_buffer.vhd.
+ - The actual data width depends on the generic g_data_w in
+ diag_data_buffer.vhd. The value of unused MSBits is undefined.
+
+
+ Memory map REG_DIAG_DATA_BUFFER (one for each stream like the RAM above)
+
+ +----------------------------------------------------------------------------+
+ | byte 3 | byte 2 | byte 1 | byte 0 | wi |
+ |----------------------------------------------------------------------------|
+ | sync_cnt[31:0] | 0 RO (Version 0 and 1) |
+ | word_cnt[31:0] | 1 RO (Version 0 and 1) |
+ | R = valid_cnt[31:0] W = arm_enable | 2 RW (Version 1 only) |
+ | reg_sync_delay[31:0] | 3 RW (Version 1 only) |
+ | RESERVED | 4 (Version 1 only) |
+ | RESERVED | 5 (Version 1 only) |
+ | RESERVED | 6 (Version 1 only) |
+ | version[31:0] | 7 RO (Version 1 only) |
+ +----------------------------------------------------------------------------+
+
+
+ There are 3 access_modes of operation of the data_buffer.
+ Version 0 supports access_Mode 1 and access_Mode 2
+ Version 1 supports access_Mode 1, access_Mode 2 and access_Mode 3
+
+ (1) NON-SYNC access_MODE: g_use_in_sync = FALSE
+ In this access_mode the first g_nof_data valid data input words are stored in the
+ data buffer. A new set of data will be stored when the last word is read
+ from the buffer via the MM interface.
+
+ (2) SYNC-access_MODE: g_use_in_sync = TRUE and reg_sync_delay = 0
+ On every received sync pulse a number of g_nof_data valid words are written
+ to the databuffer. Data will be overwritten on every new sync pulse. It is
+ up to the user to read out the data in time in between two sync pulses
+
+ (3) ARM-access_MODE: g_use_in_sync = TRUE and reg_sync_delay | 0
+ First the reg_sync_delay should be written with a desired delay value. Then
+ the arm REG must be written. After being armed the databuffer will wait
+ for the first sync pulse to arrive. When it has arrived it will wait for
+ reg_sync_delay valid cycles before g_nof_data valid words are written to the
+ databuffer. The data can then be read out through the MM interface. New data
+ will only be written if the databuffer is being armed again.
+
+ - Sync_cnt contains the nof times the buffer (ST) has received a sync pulse
+ since the last MM read (cleared when the last data word from the buffer is
+ read);
+ - Word_cnt indicates the number of word currently (ST) written in the buffer.
+ Cleared on (ST) re-write of buffer.
+ - valid_cnt contains the number of valid cycles since the last sync pulse.
+ Cleared on every sync pulse.
+ - arm_enable. Write to this REG to arm the system. After the system is
+ armed the next syn pulse will truigger the acquisition of data.
+ - reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
+ before the data is written to the databuffer.
+ - version contains the version number of the databuffer peripheral."
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index f5dd5eccc8c00cccbdc16cbffe8c61f4adace468..5bc3ecf934cdc0a2d15ffee6e91e3b9e7fa5390a 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -176,7 +176,7 @@ BEGIN
dp_clk <= i_dp_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..1c6e7a3bb2e6fcde98cd871db2aad69062201d07
--- /dev/null
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -0,0 +1,69 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : dp
+hdl_library_description: " This is the description for the dp package "
+
+peripherals:
+ -
+ peripheral_name: dp_bsn_align
+
+ parameters:
+ - { name: g_nof_input, value : 2 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_dp_bsn_align
+ slave_prefix : DP
+ slave_name : BSN_ALIGN
+ slave_postfix: REG
+ number_of_slaves: g_nof_input
+ slave_type : REG
+ fields:
+ -
+ field_name : Enable
+ width : 1
+ address_offset : 0x0
+ field_description: |
+ "Input enable register for input 0. If set to 0 the input is discarded from alignment.
+ If set to 1 the corresopnding input is taken into account."
+ slave_discription: " "
+
+ peripheral_description: "This is the BSN aligner"
+
+ -
+ peripheral_name: dp_fifo_fill
+ parameters:
+ - { name : g_nof_streams, value: 3 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_dp_fifo_fill
+ slave_prefix : DP
+ slave_name : FIFO_FILL
+ slave_postfix: REG
+ number_of_slaves: g_nof_streams
+ slave_type : REG
+ fields:
+ -
+ field_name : fifo_used_words
+ access_mode : RO
+ address_offset : 0x0
+ field_description: "Register reflects the currently used nof words on the fifo."
+ -
+ field_name : fifo_status
+ width : 2
+ access_mode : RO
+ address_offset : 0x1
+ field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
+ -
+ field_name : max_fifo_used_words
+ access_mode : RO
+ address_offset : 0x2
+ field_description: |
+ "Register contains the maximum number of words that have been in the fifo.
+ Will be cleared after it has been read."
+ slave_discription: ""
+
+ peripheral_description: "This is the MM slave version of the dp_fifo_fill component."
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index f70babcff017d97ab122c1f8c0f700cc838dd16a..f46490feb44fd997f9a315dac9eba97d1428790d 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -37,7 +37,7 @@ PACKAGE mm_file_unb_pkg IS
CONSTANT c_mmf_unb_nof_pn : NATURAL := c_mmf_unb_nof_fn + c_mmf_unb_nof_bn; -- = 8
-- use fixed central directory to ease use of Python test case with Modelsim
- CONSTANT c_mmf_unb_file_path : STRING := "$UNB/Software/python/sim/";
+ CONSTANT c_mmf_unb_file_path : STRING := "$HDL_IOFILE_SIM_DIR/";
-- create mmf file prefix that is unique per slave
FUNCTION mmf_unb_file_prefix(sys: t_c_mmf_unb_sys; node: NATURAL) RETURN STRING;
diff --git a/libraries/dsp/bf/bf.peripheral.yaml b/libraries/dsp/bf/bf.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b4359c3404086da5bf4daf68dd0b665f57608799
--- /dev/null
+++ b/libraries/dsp/bf/bf.peripheral.yaml
@@ -0,0 +1,94 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : bf
+hdl_library_description: " This is the description for the bf package "
+
+peripherals:
+ - peripheral_name: bf_unit
+
+ parameters:
+ - { name: g_bf.in_weights_w , value: 16 }
+ - { name: g_bf.nof_weights , value: 256 }
+ - { name: g_bf.nof_signal_paths , value: 64 }
+ - { name: g_bf.nof_subbands , value: 24 }
+ - { name: g_bf.nof_input_streams , value: 16 }
+ - { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams }
+
+ slave_ports:
+ -
+ # ram_bf_weights
+ slave_prefix : BF
+ slave_name : WEIGHTS
+ slave_postfix: RAM
+ number_of_slaves: g_bf.nof_weights
+ slave_type: RAM
+ fields:
+ -
+ field_name : bf_weights
+ width : g_bf.in_weights_w * c_nof_complex
+
+ number_of_fields: g_bf.nof_signal_paths
+ field_description: |
+ "Contains the weights.
+ The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+ slave_discription: >
+ " "
+
+ -
+ # ram_ss_ss_wide
+ slave_prefix : BF
+ slave_name : SS_SS_WIDE
+ slave_postfix: RAM
+ number_of_slaves: g_bf.nof_weights
+ slave_type: RAM
+ fields:
+ -
+ field_name : ss_ss_wide
+ width : 32
+ number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+ field_description: |
+ "Contains the addresses to select from the stored subbands."
+ slave_discription: >
+ " "
+
+ -
+ # ram_st_sst_bf
+ slave_prefix : BF
+ slave_name : ST_SST
+ slave_postfix: RAM
+ number_of_slaves: g_bf.nof_weights
+ slave_type: RAM
+ fields:
+ -
+ field_name : st_sst_bf
+ width : 56
+ number_of_fields: 512
+ access_mode : RO
+ field_description: |
+ "Contains the weights.
+ The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+ slave_discription: >
+
+ -
+ # reg_st_sst_bf
+ slave_prefix : BF
+ slave_name : ST_SST
+ slave_postfix: REG
+ number_of_slaves: 1
+ slave_type: REG
+ fields:
+ -
+ field_name : treshold
+ address_offset: 0x0
+ field_description : |
+ "When the treshold register is set to 0 the statistics will be auto-correlations.
+ In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
+ for the a-input of the multiplier.
+ The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
+ slave_discription: >
+ " "
+
+ peripheral_description: |
+ "This is the beamformer unit"
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index aeff190347ba10b63d455fdba7fd03f3f7089899..33be7018ca91af729653e4b5ea6a906d2dd60e22 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -169,7 +169,7 @@ BEGIN
eth1g_tse_clk <= i_tse_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index c43cbeca4faa08defe29a5f662848ba3475f00ee..48ca14509ed8e369f8bdae0dbdb1157cdd1cd30b 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -198,7 +198,7 @@ BEGIN
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
diff --git a/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a48573c686828c7ff18e53b0a8e3c6cd8e66bab1
--- /dev/null
+++ b/libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml
@@ -0,0 +1,121 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : fringe_stop
+hdl_library_description: " This is the description for the finge_stop library "
+
+peripherals:
+ -
+ peripheral_name: fringe_stop_unit
+
+ parameters:
+ - { name: g_nof_channels, value: 256 }
+ - { name: g_fs_offset_w , value: 10 }
+ - { name: g_fs_step_w , value: 17 }
+
+ slave_ports:
+ -
+ # actual hdl name: ram_fringe_stop_step
+ slave_prefix : FRINGE_STOP
+ slave_name : STEP
+ slave_postfix: RAM
+ slave_type : RAM
+ fields:
+ -
+ field_name : fringe_stop_step
+ width: g_fs_step_w
+ number_of_fields: g_nof_channels
+ field_description: |
+ "Contains the step size for all nof_channels channels."
+ slave_discription: " "
+
+ -
+ # actual hdl name: fringe_stop_offset
+ slave_prefix : FRINGE_STOP
+ slave_name : OFFSET
+ slave_postfix: RAM
+ slave_type : RAM
+ fields:
+ -
+ field_name: fringe_stop_offset
+ width: g_fs_offset_w
+ number_of_fields: g_nof_channels
+ field_description: |
+ "Contains the offset for all nof_channels channels."
+ slave_discription: " "
+
+ peripheral_description: |
+ "The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step.
+ The offset and step are used to calculate an index that is used to select a certain phase from a look-up table. The look-up
+ table contains a series of complex values that are based on a sinewave. The length of the look-up table is determined by the
+ width of the offset RAM (offset_w). If offset_w = 10 then the length of the look-up table is 2^offset_w=1024. In that case
+ the look-up table contains 1024 complex values that make one sine-wave period.
+
+ The index is determined as follows:
+
+ index(t) = (offset + step*t) MOD 2^offset_w
+
+ Where t ranges from 0 to Tmax-1. Tmax is the number of samples that fit in the control interval (the sync interval).
+ The fringe stop peripheral is capable to process 1 or more channels in series (nof_channels).
+
+ Accumulation Register
+ The accumulation register that maintains the accumulated step value is flushed by the sync pulse in the system.
+ The accumulation register in the Apertif case is 31 bit wide. For the additon of the offset and the accumulated step the
+ 10 (offset_w) highest bit of the accumulated value are used --> offset(9:0) + step_accumulated(30:21).
+
+ RAMs
+ The fringe stop interface is facilitated by two RAMs:
+
+ -RAM_FRINGE_STOP_OFFSET
+ -RAM_FRINGE_STOP_STEP
+
+ Both RAMs are implemented as dual-page RAMs.The page swap is triggered by the sync-pulse. The VHDL is always accessing
+ the page that is NOT accessible for the software and vice-versa. This means that the values that are written to the RAMs
+ will only be actually used in the following sync-interval:
+
+
+ A| _ T0 _ T1 _ T2
+ A| sync __| |___________________________| |___________________________| |________________________
+ A| | VHDL uses data T0 | VHDL uses data T1 | VHDL uses data T2
+ A| | Software writes data T1 | Software writes data T2 | Software writes data T3
+ A| | | |
+ A| page_swap page_swap page_swap
+
+
+ The software should be sure to write the next set of data before the sync_interval expires. Keeping track of the
+ synchronization with the sync-pulse can be done, using one of the BSN Monitors in the system. In the Apertif system
+ the BSN Monitor at the input of the beamformer can be used.
+
+ The number_of_fields of both RAMs is determined by the number of unique channels that ought to be processed.
+
+ RAM_FRINGE_STOP_OFFSET
+ This RAM contains the offset values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
+ defined by the offset_w.
+
+ +-----------------------------------------+
+ | RAM_address | RAM_content |
+ |-----------------------------------------|
+ | 0x0 | Offset_Channel_0 |
+ | 0x1 | Offset_Channel_1 |
+ | 0x2 | Offset_Channel_2 |
+ | 0x3 | Offset_Channel_3 |
+ | .. | .. |
+ | .. | Offset_Channel_Max-1 |
+ +-----------------------------------------+
+
+ RAM_FRINGE_STOP_STEP
+ This RAM contains the step size values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
+ specified by the step_w.
+
+ +-----------------------------------------+
+ | RAM_address | RAM_content |
+ |-----------------------------------------|
+ | 0x0 | Step_Channel_0 |
+ | 0x1 | Step_Channel_1 |
+ | 0x2 | Step_Channel_2 |
+ | 0x3 | Step_Channel_3 |
+ | .. | .. |
+ | .. | Step_Channel_Max-1 |
+ +-----------------------------------------+"
+
diff --git a/libraries/io/epcs/epcs.peripheral.yaml b/libraries/io/epcs/epcs.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..50045e05a6e1c132f0ab60ce0cc503ef82c2288f
--- /dev/null
+++ b/libraries/io/epcs/epcs.peripheral.yaml
@@ -0,0 +1,135 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : epcs
+hdl_library_description: " This is the description for the epcs package "
+
+peripherals:
+
+ # epcs_reg
+ -
+ peripheral_name: epcs_reg
+
+ parameters:
+ - {name: "g_sim_flash_model", value: TRUE}
+
+ slave_ports:
+ -
+ # actual hdl name: epcs_reg
+ slave_prefix : EPCS
+ slave_name : EPCS
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : addr
+ width : 24
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " address to write to or read from "
+
+ -
+ field_name : rden
+ width : 1
+ access_mode : WO
+ address_offset: 0x1
+ field_description: " Read enable bit "
+
+ -
+ field_name : read_bit
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x2
+ field_description: " Read bit "
+
+ -
+ field_name : write_bit
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x3
+ field_description: " Write bit "
+
+ -
+ field_name : sector_erase
+ width : 1
+ access_mode : WO
+ address_offset: 0x4
+ field_description: " Sector erase bit "
+
+ -
+ field_name : busy
+ width : 1
+ access_mode : RO
+ address_offset: 0x5
+ field_description: " busy "
+
+ slave_description: " Read and write access to flash "
+
+ # actual hdl name: mms_dp_fifo_to_mm
+ -
+ slave_prefix : EPCS
+ slave_name : DPMM_CTRL
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : ctrl
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
+
+ -
+ slave_prefix : EPCS
+ slave_name : DPMM_DATA
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : data
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
+
+ # actual hdl name: mms_dp_fifo_from_mm
+ -
+ slave_prefix : EPCS
+ slave_name : MMDP_CTRL
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : ctrl
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
+
+ -
+ slave_prefix : EPCS
+ slave_name : MMDP_DATA
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : data
+ width : 32
+ access_mode : RW
+ address_offset: 0x0
+ field_description: " "
+
+ peripheral_description: |
+ "wi Bits SE R/W Name Default Description |REG_EPCS|
+ =============================================================================
+ 0 [23..0] WO addr 0x0 Address to write to/read from
+ 1 [0] WO rden 0x0 Read enable
+ 2 [0] PW WE read 0x0 Read
+ 3 [0] PW WE write 0x0 Write
+ 4 [0] WO sector_erase 0x0 Sector erase
+ 5 [0] RO busy 0x0 Busy
+ ============================================================================="
+
\ No newline at end of file
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index d48b4e138bc67ad1cf28af1fc924b441e98c0526..3504584981f117150c4db5ccc850942864c3d729 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -419,7 +419,7 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
BEGIN
----------------------------------------------------------------------------
- -- MM <-> file I/O for simulation. The files are created in $UPE_GEAR/sim.
+ -- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f8a30232682a1caec7d26f287072ff4602e6d50d
--- /dev/null
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -0,0 +1,66 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : eth
+hdl_library_description: " This is the description for the eth package "
+
+peripherals:
+ -
+ peripheral_name: eth1g
+
+ parameters:
+ - { name: c_eth_ram_nof_words, value: 1024 }
+ #g_technology: c_tech_select_default
+ #g_ETH_PHY : "LVDS"
+
+ slave_ports:
+ -
+ # actual hdl name: reg_tse
+ slave_prefix : ETH
+ slave_name : TSE
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : status
+ access_mode : RO
+ address_offset : 0x0
+ number_of_fields: 1024
+ field_description: |
+ " reg tse "
+ slave_description: ""
+ -
+ # actual hdl name: reg
+ slave_prefix : ETH
+ slave_name : REG
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : status
+ access_mode : RO
+ address_offset : 0x0
+ number_of_fields: 11
+ field_description: " reg registers "
+ slave_description: " "
+ -
+ # actual hdl name: ram
+ slave_prefix : ETH
+ slave_name : RAM
+ slave_postfix: RAM
+ slave_type : RAM
+ fields:
+ -
+ field_name : ram
+ number_of_fields: c_eth_ram_nof_words
+ field_description: |
+ "Contains the Waveform data for the data-streams to be send"
+ slave_description: " "
+
+ peripheral_description: |
+ "
+ Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
+ packets for the streaming channels are directed based on the UDP port
+ number and all other packets are transfered to the default control channel."
+
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 553407d82e6b40c953da4f1d08dcc042f96e40aa..a9c17c9c3bbbf81bc2fed71ffd2886dce1691fe7 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -44,6 +44,11 @@ regression_test_vhdl =
[modelsim_project_file]
-
+modelsim_copy_files =
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
+quartus_copy_files =
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
\ No newline at end of file
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index 21621a58dff936de7f1420b870172d9caca69434..78cfca72bd307a5d516047cf40a897c494e8fc9a 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -10,9 +10,9 @@
#
#
-# request TCL package from ACDS 17.0
+# request TCL package from ACDS 18.0
#
-package require -exact qsys 17.0
+package require -exact qsys 18.0
#
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
index 21621a58dff936de7f1420b870172d9caca69434..78cfca72bd307a5d516047cf40a897c494e8fc9a 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
@@ -10,9 +10,9 @@
#
#
-# request TCL package from ACDS 17.0
+# request TCL package from ACDS 18.0
#
-package require -exact qsys 17.0
+package require -exact qsys 18.0
#
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..78cfca72bd307a5d516047cf40a897c494e8fc9a
--- /dev/null
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl
@@ -0,0 +1,530 @@
+# TCL File Generated by Component Editor 17.0.1
+# Thu Jul 13 11:06:59 CEST 2017
+# DO NOT MODIFY
+
+
+#
+# avs2_eth_coe "avs2_eth_coe" v1.0
+# ASTRON 2017.07.13.11:06:59
+# MM slave port to conduit for the ETH module
+#
+
+#
+# request TCL package from ACDS 18.0
+#
+package require -exact qsys 18.0
+
+
+#
+# module avs2_eth_coe
+#
+set_module_property DESCRIPTION "MM slave port to conduit for the ETH module"
+set_module_property NAME avs2_eth_coe
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Uniboard
+set_module_property AUTHOR ASTRON
+set_module_property DISPLAY_NAME avs2_eth_coe
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL avs2_eth_coe
+set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd TOP_LEVEL_FILE
+add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
+add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
+add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
+add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd
+
+add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"
+set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file avs2_eth_coe.vhd VHDL PATH avs2_eth_coe.vhd
+add_fileset_file common_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_pkg.vhd
+add_fileset_file dp_stream_pkg.vhd VHDL PATH ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd
+add_fileset_file tech_tse_pkg.vhd VHDL PATH ../../../../technology/tse/tech_tse_pkg.vhd
+add_fileset_file eth_pkg.vhd VHDL PATH eth_pkg.vhd
+add_fileset_file common_network_layers_pkg.vhd VHDL PATH ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point mm
+#
+add_interface mm clock end
+set_interface_property mm clockRate 0
+set_interface_property mm ENABLED true
+set_interface_property mm EXPORT_OF ""
+set_interface_property mm PORT_NAME_MAP ""
+set_interface_property mm CMSIS_SVD_VARIABLES ""
+set_interface_property mm SVD_ADDRESS_GROUP ""
+
+add_interface_port mm csi_mm_clk clk Input 1
+
+
+#
+# connection point mm_reset
+#
+add_interface mm_reset reset end
+set_interface_property mm_reset associatedClock mm
+set_interface_property mm_reset synchronousEdges DEASSERT
+set_interface_property mm_reset ENABLED true
+set_interface_property mm_reset EXPORT_OF ""
+set_interface_property mm_reset PORT_NAME_MAP ""
+set_interface_property mm_reset CMSIS_SVD_VARIABLES ""
+set_interface_property mm_reset SVD_ADDRESS_GROUP ""
+
+add_interface_port mm_reset csi_mm_reset reset Input 1
+
+
+#
+# connection point mms_tse
+#
+add_interface mms_tse avalon end
+set_interface_property mms_tse addressUnits WORDS
+set_interface_property mms_tse associatedClock mm
+set_interface_property mms_tse associatedReset mm_reset
+set_interface_property mms_tse bitsPerSymbol 8
+set_interface_property mms_tse bridgedAddressOffset ""
+set_interface_property mms_tse bridgesToMaster ""
+set_interface_property mms_tse burstOnBurstBoundariesOnly false
+set_interface_property mms_tse burstcountUnits WORDS
+set_interface_property mms_tse explicitAddressSpan 0
+set_interface_property mms_tse holdTime 0
+set_interface_property mms_tse linewrapBursts false
+set_interface_property mms_tse maximumPendingReadTransactions 0
+set_interface_property mms_tse maximumPendingWriteTransactions 0
+set_interface_property mms_tse minimumResponseLatency 1
+set_interface_property mms_tse readLatency 0
+set_interface_property mms_tse readWaitTime 1
+set_interface_property mms_tse setupTime 0
+set_interface_property mms_tse timingUnits Cycles
+set_interface_property mms_tse transparentBridge false
+set_interface_property mms_tse waitrequestAllowance 0
+set_interface_property mms_tse writeWaitTime 0
+set_interface_property mms_tse ENABLED true
+set_interface_property mms_tse EXPORT_OF ""
+set_interface_property mms_tse PORT_NAME_MAP ""
+set_interface_property mms_tse CMSIS_SVD_VARIABLES ""
+set_interface_property mms_tse SVD_ADDRESS_GROUP ""
+
+add_interface_port mms_tse mms_tse_address address Input 10
+add_interface_port mms_tse mms_tse_write write Input 1
+add_interface_port mms_tse mms_tse_read read Input 1
+add_interface_port mms_tse mms_tse_writedata writedata Input 32
+add_interface_port mms_tse mms_tse_readdata readdata Output 32
+add_interface_port mms_tse mms_tse_waitrequest waitrequest Output 1
+set_interface_assignment mms_tse embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_tse embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_tse embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_tse embeddedsw.configuration.isPrintableDevice false
+
+
+#
+# connection point mms_reg
+#
+add_interface mms_reg avalon end
+set_interface_property mms_reg addressUnits WORDS
+set_interface_property mms_reg associatedClock mm
+set_interface_property mms_reg associatedReset mm_reset
+set_interface_property mms_reg bitsPerSymbol 8
+set_interface_property mms_reg bridgedAddressOffset ""
+set_interface_property mms_reg bridgesToMaster ""
+set_interface_property mms_reg burstOnBurstBoundariesOnly false
+set_interface_property mms_reg burstcountUnits WORDS
+set_interface_property mms_reg explicitAddressSpan 0
+set_interface_property mms_reg holdTime 0
+set_interface_property mms_reg linewrapBursts false
+set_interface_property mms_reg maximumPendingReadTransactions 0
+set_interface_property mms_reg maximumPendingWriteTransactions 0
+set_interface_property mms_reg minimumResponseLatency 1
+set_interface_property mms_reg readLatency 1
+set_interface_property mms_reg readWaitStates 0
+set_interface_property mms_reg readWaitTime 0
+set_interface_property mms_reg setupTime 0
+set_interface_property mms_reg timingUnits Cycles
+set_interface_property mms_reg transparentBridge false
+set_interface_property mms_reg waitrequestAllowance 0
+set_interface_property mms_reg writeWaitTime 0
+set_interface_property mms_reg ENABLED true
+set_interface_property mms_reg EXPORT_OF ""
+set_interface_property mms_reg PORT_NAME_MAP ""
+set_interface_property mms_reg CMSIS_SVD_VARIABLES ""
+set_interface_property mms_reg SVD_ADDRESS_GROUP ""
+
+add_interface_port mms_reg mms_reg_address address Input 4
+add_interface_port mms_reg mms_reg_write write Input 1
+add_interface_port mms_reg mms_reg_read read Input 1
+add_interface_port mms_reg mms_reg_writedata writedata Input 32
+add_interface_port mms_reg mms_reg_readdata readdata Output 32
+set_interface_assignment mms_reg embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_reg embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_reg embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_reg embeddedsw.configuration.isPrintableDevice false
+
+
+#
+# connection point mms_ram
+#
+add_interface mms_ram avalon end
+set_interface_property mms_ram addressUnits WORDS
+set_interface_property mms_ram associatedClock mm
+set_interface_property mms_ram associatedReset mm_reset
+set_interface_property mms_ram bitsPerSymbol 8
+set_interface_property mms_ram bridgedAddressOffset ""
+set_interface_property mms_ram bridgesToMaster ""
+set_interface_property mms_ram burstOnBurstBoundariesOnly false
+set_interface_property mms_ram burstcountUnits WORDS
+set_interface_property mms_ram explicitAddressSpan 0
+set_interface_property mms_ram holdTime 0
+set_interface_property mms_ram linewrapBursts false
+set_interface_property mms_ram maximumPendingReadTransactions 0
+set_interface_property mms_ram maximumPendingWriteTransactions 0
+set_interface_property mms_ram minimumResponseLatency 1
+set_interface_property mms_ram readLatency 2
+set_interface_property mms_ram readWaitStates 0
+set_interface_property mms_ram readWaitTime 0
+set_interface_property mms_ram setupTime 0
+set_interface_property mms_ram timingUnits Cycles
+set_interface_property mms_ram transparentBridge false
+set_interface_property mms_ram waitrequestAllowance 0
+set_interface_property mms_ram writeWaitTime 0
+set_interface_property mms_ram ENABLED true
+set_interface_property mms_ram EXPORT_OF ""
+set_interface_property mms_ram PORT_NAME_MAP ""
+set_interface_property mms_ram CMSIS_SVD_VARIABLES ""
+set_interface_property mms_ram SVD_ADDRESS_GROUP ""
+
+add_interface_port mms_ram mms_ram_address address Input 10
+add_interface_port mms_ram mms_ram_write write Input 1
+add_interface_port mms_ram mms_ram_read read Input 1
+add_interface_port mms_ram mms_ram_writedata writedata Input 32
+add_interface_port mms_ram mms_ram_readdata readdata Output 32
+set_interface_assignment mms_ram embeddedsw.configuration.isFlash 0
+set_interface_assignment mms_ram embeddedsw.configuration.isMemoryDevice false
+set_interface_assignment mms_ram embeddedsw.configuration.isNonVolatileStorage false
+set_interface_assignment mms_ram embeddedsw.configuration.isPrintableDevice false
+
+
+#
+# connection point interrupt
+#
+add_interface interrupt interrupt end
+set_interface_property interrupt associatedAddressablePoint mms_reg
+set_interface_property interrupt associatedClock mm
+set_interface_property interrupt associatedReset mm_reset
+set_interface_property interrupt bridgedReceiverOffset ""
+set_interface_property interrupt bridgesToReceiver ""
+set_interface_property interrupt ENABLED true
+set_interface_property interrupt EXPORT_OF ""
+set_interface_property interrupt PORT_NAME_MAP ""
+set_interface_property interrupt CMSIS_SVD_VARIABLES ""
+set_interface_property interrupt SVD_ADDRESS_GROUP ""
+
+add_interface_port interrupt ins_interrupt_irq irq Output 1
+
+
+#
+# connection point reset
+#
+add_interface reset conduit end
+set_interface_property reset associatedClock ""
+set_interface_property reset associatedReset ""
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset coe_reset_export export Output 1
+
+
+#
+# connection point clk
+#
+add_interface clk conduit end
+set_interface_property clk associatedClock ""
+set_interface_property clk associatedReset ""
+set_interface_property clk ENABLED true
+set_interface_property clk EXPORT_OF ""
+set_interface_property clk PORT_NAME_MAP ""
+set_interface_property clk CMSIS_SVD_VARIABLES ""
+set_interface_property clk SVD_ADDRESS_GROUP ""
+
+add_interface_port clk coe_clk_export export Output 1
+
+
+#
+# connection point tse_address
+#
+add_interface tse_address conduit end
+set_interface_property tse_address associatedClock ""
+set_interface_property tse_address associatedReset ""
+set_interface_property tse_address ENABLED true
+set_interface_property tse_address EXPORT_OF ""
+set_interface_property tse_address PORT_NAME_MAP ""
+set_interface_property tse_address CMSIS_SVD_VARIABLES ""
+set_interface_property tse_address SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_address coe_tse_address_export export Output 10
+
+
+#
+# connection point tse_write
+#
+add_interface tse_write conduit end
+set_interface_property tse_write associatedClock ""
+set_interface_property tse_write associatedReset ""
+set_interface_property tse_write ENABLED true
+set_interface_property tse_write EXPORT_OF ""
+set_interface_property tse_write PORT_NAME_MAP ""
+set_interface_property tse_write CMSIS_SVD_VARIABLES ""
+set_interface_property tse_write SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_write coe_tse_write_export export Output 1
+
+
+#
+# connection point tse_read
+#
+add_interface tse_read conduit end
+set_interface_property tse_read associatedClock ""
+set_interface_property tse_read associatedReset ""
+set_interface_property tse_read ENABLED true
+set_interface_property tse_read EXPORT_OF ""
+set_interface_property tse_read PORT_NAME_MAP ""
+set_interface_property tse_read CMSIS_SVD_VARIABLES ""
+set_interface_property tse_read SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_read coe_tse_read_export export Output 1
+
+
+#
+# connection point tse_writedata
+#
+add_interface tse_writedata conduit end
+set_interface_property tse_writedata associatedClock ""
+set_interface_property tse_writedata associatedReset ""
+set_interface_property tse_writedata ENABLED true
+set_interface_property tse_writedata EXPORT_OF ""
+set_interface_property tse_writedata PORT_NAME_MAP ""
+set_interface_property tse_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property tse_writedata SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_writedata coe_tse_writedata_export export Output 32
+
+
+#
+# connection point tse_readdata
+#
+add_interface tse_readdata conduit end
+set_interface_property tse_readdata associatedClock ""
+set_interface_property tse_readdata associatedReset ""
+set_interface_property tse_readdata ENABLED true
+set_interface_property tse_readdata EXPORT_OF ""
+set_interface_property tse_readdata PORT_NAME_MAP ""
+set_interface_property tse_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property tse_readdata SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_readdata coe_tse_readdata_export export Input 32
+
+
+#
+# connection point tse_waitrequest
+#
+add_interface tse_waitrequest conduit end
+set_interface_property tse_waitrequest associatedClock ""
+set_interface_property tse_waitrequest associatedReset ""
+set_interface_property tse_waitrequest ENABLED true
+set_interface_property tse_waitrequest EXPORT_OF ""
+set_interface_property tse_waitrequest PORT_NAME_MAP ""
+set_interface_property tse_waitrequest CMSIS_SVD_VARIABLES ""
+set_interface_property tse_waitrequest SVD_ADDRESS_GROUP ""
+
+add_interface_port tse_waitrequest coe_tse_waitrequest_export export Input 1
+
+
+#
+# connection point reg_address
+#
+add_interface reg_address conduit end
+set_interface_property reg_address associatedClock ""
+set_interface_property reg_address associatedReset ""
+set_interface_property reg_address ENABLED true
+set_interface_property reg_address EXPORT_OF ""
+set_interface_property reg_address PORT_NAME_MAP ""
+set_interface_property reg_address CMSIS_SVD_VARIABLES ""
+set_interface_property reg_address SVD_ADDRESS_GROUP ""
+
+add_interface_port reg_address coe_reg_address_export export Output 4
+
+
+#
+# connection point reg_write
+#
+add_interface reg_write conduit end
+set_interface_property reg_write associatedClock ""
+set_interface_property reg_write associatedReset ""
+set_interface_property reg_write ENABLED true
+set_interface_property reg_write EXPORT_OF ""
+set_interface_property reg_write PORT_NAME_MAP ""
+set_interface_property reg_write CMSIS_SVD_VARIABLES ""
+set_interface_property reg_write SVD_ADDRESS_GROUP ""
+
+add_interface_port reg_write coe_reg_write_export export Output 1
+
+
+#
+# connection point reg_read
+#
+add_interface reg_read conduit end
+set_interface_property reg_read associatedClock ""
+set_interface_property reg_read associatedReset ""
+set_interface_property reg_read ENABLED true
+set_interface_property reg_read EXPORT_OF ""
+set_interface_property reg_read PORT_NAME_MAP ""
+set_interface_property reg_read CMSIS_SVD_VARIABLES ""
+set_interface_property reg_read SVD_ADDRESS_GROUP ""
+
+add_interface_port reg_read coe_reg_read_export export Output 1
+
+
+#
+# connection point reg_writedata
+#
+add_interface reg_writedata conduit end
+set_interface_property reg_writedata associatedClock ""
+set_interface_property reg_writedata associatedReset ""
+set_interface_property reg_writedata ENABLED true
+set_interface_property reg_writedata EXPORT_OF ""
+set_interface_property reg_writedata PORT_NAME_MAP ""
+set_interface_property reg_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property reg_writedata SVD_ADDRESS_GROUP ""
+
+add_interface_port reg_writedata coe_reg_writedata_export export Output 32
+
+
+#
+# connection point reg_readdata
+#
+add_interface reg_readdata conduit end
+set_interface_property reg_readdata associatedClock ""
+set_interface_property reg_readdata associatedReset ""
+set_interface_property reg_readdata ENABLED true
+set_interface_property reg_readdata EXPORT_OF ""
+set_interface_property reg_readdata PORT_NAME_MAP ""
+set_interface_property reg_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property reg_readdata SVD_ADDRESS_GROUP ""
+
+add_interface_port reg_readdata coe_reg_readdata_export export Input 32
+
+
+#
+# connection point ram_address
+#
+add_interface ram_address conduit end
+set_interface_property ram_address associatedClock ""
+set_interface_property ram_address associatedReset ""
+set_interface_property ram_address ENABLED true
+set_interface_property ram_address EXPORT_OF ""
+set_interface_property ram_address PORT_NAME_MAP ""
+set_interface_property ram_address CMSIS_SVD_VARIABLES ""
+set_interface_property ram_address SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_address coe_ram_address_export export Output 10
+
+
+#
+# connection point ram_write
+#
+add_interface ram_write conduit end
+set_interface_property ram_write associatedClock ""
+set_interface_property ram_write associatedReset ""
+set_interface_property ram_write ENABLED true
+set_interface_property ram_write EXPORT_OF ""
+set_interface_property ram_write PORT_NAME_MAP ""
+set_interface_property ram_write CMSIS_SVD_VARIABLES ""
+set_interface_property ram_write SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_write coe_ram_write_export export Output 1
+
+
+#
+# connection point ram_read
+#
+add_interface ram_read conduit end
+set_interface_property ram_read associatedClock ""
+set_interface_property ram_read associatedReset ""
+set_interface_property ram_read ENABLED true
+set_interface_property ram_read EXPORT_OF ""
+set_interface_property ram_read PORT_NAME_MAP ""
+set_interface_property ram_read CMSIS_SVD_VARIABLES ""
+set_interface_property ram_read SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_read coe_ram_read_export export Output 1
+
+
+#
+# connection point ram_writedata
+#
+add_interface ram_writedata conduit end
+set_interface_property ram_writedata associatedClock ""
+set_interface_property ram_writedata associatedReset ""
+set_interface_property ram_writedata ENABLED true
+set_interface_property ram_writedata EXPORT_OF ""
+set_interface_property ram_writedata PORT_NAME_MAP ""
+set_interface_property ram_writedata CMSIS_SVD_VARIABLES ""
+set_interface_property ram_writedata SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_writedata coe_ram_writedata_export export Output 32
+
+
+#
+# connection point ram_readdata
+#
+add_interface ram_readdata conduit end
+set_interface_property ram_readdata associatedClock ""
+set_interface_property ram_readdata associatedReset ""
+set_interface_property ram_readdata ENABLED true
+set_interface_property ram_readdata EXPORT_OF ""
+set_interface_property ram_readdata PORT_NAME_MAP ""
+set_interface_property ram_readdata CMSIS_SVD_VARIABLES ""
+set_interface_property ram_readdata SVD_ADDRESS_GROUP ""
+
+add_interface_port ram_readdata coe_ram_readdata_export export Input 32
+
+
+#
+# connection point irq
+#
+add_interface irq conduit end
+set_interface_property irq associatedClock ""
+set_interface_property irq associatedReset ""
+set_interface_property irq ENABLED true
+set_interface_property irq EXPORT_OF ""
+set_interface_property irq PORT_NAME_MAP ""
+set_interface_property irq CMSIS_SVD_VARIABLES ""
+set_interface_property irq SVD_ADDRESS_GROUP ""
+
+add_interface_port irq coe_irq_export export Input 1
+
diff --git a/libraries/io/ppsh/ppsh.peripheral.yaml b/libraries/io/ppsh/ppsh.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..b9b71e89d669190ec79128165c4c5e501c1d89d0
--- /dev/null
+++ b/libraries/io/ppsh/ppsh.peripheral.yaml
@@ -0,0 +1,46 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : ppsh
+hdl_library_description: " This is the description for the finppshge_stop library "
+
+peripherals:
+ -
+ peripheral_name: ppsh
+ parameters:
+ - { name: g_cross_clock_domain, value: TRUE }
+ - { name: g_st_clk_freq, value: 200 * 10**6 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_ppsh
+ slave_prefix : PPSH
+ slave_name : PPSH
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : status
+ access_mode : RO
+ address_offset: 0x0
+ field_description: " ppsh status "
+ -
+ field_name : control
+ address_offset: 0x1
+ field_description: " ppsh control "
+ slave_discription: " "
+
+ peripheral_description: |
+ "
+ . Report PPS toggle, stable and period capture count
+ . Set dp_clk capture edge for PPS
+ Set expected period capture count for PPS stable
+ +----------------------------------------------------------------------------+
+ |31 (byte3) 24|23 (byte2) 16|15 (byte1) 8|7 (byte0) 0| wi |
+ |-----------------------------------------------------------------------|----|
+ |toggle[31], stable[30] xxx capture_cnt = [29:0]| 0 |
+ |-----------------------------------------------------------------------|----|
+ |edge[31], xxx expected_cnt = [29:0]| 1 |
+ +----------------------------------------------------------------------------+"
+
diff --git a/libraries/io/remu/remu.peripheral.yaml b/libraries/io/remu/remu.peripheral.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..51d26382f1fc9515204307ed5da0da66692d1dab
--- /dev/null
+++ b/libraries/io/remu/remu.peripheral.yaml
@@ -0,0 +1,90 @@
+schema_name : args
+schema_version: 1.0
+schema_type : peripheral
+
+hdl_library_name : remu
+hdl_library_description: " This is the description for the remu package "
+
+peripherals:
+
+ # peripheral, remu_reg
+ -
+ peripheral_name: remu_reg
+
+ parameters:
+ - { name: g_data_w, value: 24 }
+
+ slave_ports:
+ -
+ # actual hdl name: reg_remu
+ slave_prefix : WORK
+ slave_name : REMU
+ slave_postfix: REG
+ slave_type : REG
+ fields:
+ -
+ field_name : reconfigure_key
+ width : c_word_w
+ access_mode : WO
+ address_offset: 0x0
+ field_description: " reconfigure key for safety "
+
+ -
+ field_name : param
+ width : 3
+ access_mode : WO
+ address_offset: 0x1
+ radix : unsigned
+ field_description: " "
+
+ -
+ field_name : read_param
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x2
+ field_description: " read_param "
+
+ -
+ field_name : write_param
+ width : 1
+ access_mode : WO
+ side_effect : PW
+ address_offset: 0x3
+ field_description: " write_param "
+
+ -
+ field_name : data_out
+ width : g_data_w
+ access_mode : RO
+ address_offset: 0x4
+ field_description: " data_out "
+
+ -
+ field_name : data_in
+ width : g_data_w
+ access_mode : WO
+ address_offset: 0x5
+ field_description: " data_in "
+
+ -
+ field_name : busy
+ width : 1
+ access_mode : RO
+ address_offset: 0x6
+ field_description: " busy "
+
+ slave_description: " Remote Upgrade "
+
+ peripheral_description: |
+ "wi Bits R/W SE Name Default Description |REG_EPCS|
+ =============================================================================
+ 0 [31..0] WO reconfigure_key 0x0
+ 1 [2..0] WO param
+ 2 [0] WO PW read_param
+ 3 [0] WO PW write_param
+ 4 [23..0] RO data_out
+ 5 [23..0] WO data_in
+ 6 [0] RO busy
+ =============================================================================
+ "
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 4286581aace7feb963ddf2079aaf09ce9ca52ed6..02e4adb554aec475da941a60d7c76bd2fd9e58b9 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -7,6 +7,7 @@ hdl_lib_technology =
synth_files =
technology_pkg.vhd
$HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+
test_bench_files =
regression_test_vhdl =
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index 7c0f26937ab74d5506c2c6f7c86819dd716cae3a..d2c1cac94d7a915467598e00158b226912f78133 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vmap alt_em10g32_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 1ae3f80bee1f937e1768e23182102435153f2cef..48b8eadb18ffe222be00011f1a9d45c2e88cd8a9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap alt_mem_if_jtag_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index 4be28d783af91ce2de691ed2b2d25979228d60fc..0fdc6a880e087a7f252a0ffa7071d286d0bdc84f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vmap altclkctrl_180 ./work/
vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index 1d61a0aec4070b87b5c723eb203784db48758d61..d6b2ba13b801ab542ffb812499cd045bcd976b4a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vmap altera_asmi_parallel_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index 7f1f5797ff27449640d5c61ffd7dfa69411275a3..af0c7159fd9aeb9898dd708d829011e65639f3e7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_avalon_mm_bridge_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index 32aad9d5c1d887c995296b361d7591a6468b6013..edf94714dd03299d19c6edb8b7e661399c6246a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,17 +30,17 @@
#
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index a28af3acd153156cddbc199a4c42a11f405c2397..db85d837ed13d5ed34522941592c314fd4cd9a4c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_packets_to_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index 51d850450c56961cd959351d242feca34018c30f..ee66c060b0e7e1ca395e7dae50698d29a8bd7cdb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_sc_fifo_180 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index f779ec921f150c5785ca9083eb10327c2afdbebd..1a6e4e1ee4bb0e5a2c60a0180f457e2140ab51eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_bytes_to_packets_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index 288cfc78e3977b6ed4cee998b70b950a4217bb55..5399369f80dc9e53407739de92814c1c9cc6cd84 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_packets_to_bytes_180 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 04119490cc72a68a433aaa8b6ec7cbdc1b302d07..543fd5e973a9516aa61464633a21b1da9a5850c9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,42 +29,42 @@
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_emif_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_ebfu2ha.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.v" -work altera_emif_180
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
@@ -110,52 +110,52 @@ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_24
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index ab5916d893518abc4e4f33a3bb050bf85bbf8a9f..15a326cec8dafbcca19edd4ae0e243717e06c3b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 495f63d7f66fdbc97e489ec2a0b6cb76dff03f91..385052319b67e2009b1716c5e17db4df155d65a6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index 392ed02a9ed2909aa46cb32251acb20a9aac4133..a5c3c36590b3094a82f565e9245dee42e7ecbd76 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
vmap altera_eth_tse_180 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd" -work altera_eth_tse_180
# tse_sgmii_lvds
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd" -work altera_eth_tse_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index decc49bbd68243c20d01fd01aa6170e8f675e4bd..ebfe3676cb19cb08a431b9203e96a6590c0d6bfe 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_avalon_arbiter_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 53eec840307e3dddb80d749be624136d23631885..358035beda539eb04f5474b0b081a44f89b8bf16 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_mac_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 8bafa44ba2986bdb60297ae97de15809324ed787..7bb7d7873ed59c1df6cc54ff92de5c988dd65190 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 783b7647943c93cb49d9efab106c087081018ee3..01f18f57979d83e0f571442af961ae5312ee8a2a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 60d253da4700e6f78653bbccb2cccb6f3c425296..5f0cbdfbe7f9ec6e8e393ea20b8a4590cd96e6ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
@@ -39,7 +39,7 @@ vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index 7e1cd85b20e9aa5f38f610eaf4ec52c83c92ca01..c5d8719befd1072ee3d2bd73432fe5b382afa189 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
@@ -42,7 +42,7 @@ vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 555b4b1dc1acfb37562276564adaf388a2748b87..7d2db270093e09c09dc540b0c577063d6cc9a345 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -30,12 +30,12 @@
vmap altera_iopll_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index cbcb8e1c93c8a0bc05fcade73c1db535bddc2cb5..8a6590e8bfa054ded07453f84d72a7fb3b49ad07 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,8 +30,8 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_ip_col_if_180 ./work/
- vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_bnb3mmy.v" -work altera_ip_col_if_180
+ vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_jvd2zcq.v" -work altera_ip_col_if_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 8ef738a50d0a4127a5c7061e6b62699208add475..7855db26f8e5a63f80266935f967b88efec513a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_jtag_dc_streaming_180 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index b2c37f6a32e1cb0541a0684ee65e98fbdc317b23..0638a7a9520818a6dc10f6621e4bd549eee72d7a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_180 ./work/
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd" -work altera_lvds_180
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd" -work altera_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index 007e68b3552f5b8ba2ab72cda7fdb9201be82d00..763b27886008cbbb58ceef4c7af44f8475861e43 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,12 +27,12 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_core20_180 ./work/
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
+ vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
+ vlog "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_5a5vzei.vhd" -work altera_lvds_core20_180
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
+ vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
+ vlog "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_kmpu4hy.vhd" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index 35e558134d0ba248367ca538034ed85615fad1ab..80bd106da1914b57491732edf57ce30133229073 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_master_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index 8e0c1568b518869cea072ae96e89b1b586c5d40e..abeccdc26435224da3598c2864522aa281d814b5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_slave_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 5079b120b623ef648fc60acbe22f4903539cce71..260516ca230f890a50041bc00838d86108f880ff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index 9501b499a48ffc02fda0766728a39867d88192e5..4923e9411fd1cb74b2162c30701fad84431b389b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 11bc0e4488a765e20b8f411acf03eb0427925476..27a2935517fe106c7374ae001c78310471dcb8ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 3677b0d802b257e01957060a0d8d60ab837c1e06..56f7ad4cbbda4691a6b9506ad554fb48c9be9d4b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_reset_controller_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index 71be275f7fec509f9843550d70be6af80de45e1d..abf16a6330d3a5ff6fe320552e9448b3621d882f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_180 ./work/
@@ -50,6 +50,6 @@ vmap altera_xcvr_atx_pll_a10_180 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index de3daa636de26cea6160d610e6abf7cc20d85452..278e32120b0b7699dc9134174091aababe1f8232 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vmap altera_xcvr_fpll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 52b59ba51f260ca5b8e1125f695ee47a6c97f242..55ea004c209d891beb081b060bb31ce7764c2f02 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_180 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48//sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -64,35 +64,35 @@ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbas
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_48
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_24
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_12
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_4
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_3
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# tse_sgmii_gx
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index efa554752b5b63b0f851024a8b4d08322d0964c4..687d9bf2eb56786c3ce70397b91a7cc46b65b486 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vmap altera_xcvr_reset_control_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index 1a9afe12391e5cf7f444637ea4e807d215fb7c66..79d78a02f240dca1c415e8d0655f644126eb3838 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap channel_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index d0311d5b15da9a9e386885effc08df8f3e2f7f1f..dd0ebe9a6983d3c418dc741ba141c5c6e0a65899 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,10 +30,10 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap timing_adapter_180 ./work/
- vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_osazali.sv" -work timing_adapter_180
+ vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_ewif6gi.sv" -work timing_adapter_180
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 1dd44233827b9024d1843aefddae3c100fd659ca..3d395b250cfca9e836d1b0c2b0e1ad56f47e5551 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 2fb36c8f2837d83cd6a14e4d60c6d4860790171a..e4bf3a3d8940c34b163531350cf77e5c6402bdb5 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index ba381883b7ff53eea294476ed4c7964f385da470..cf358c071bf54f072d98f0b63121a4f689d0a5ec 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vmap altmult_complex_180 ./work/
vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
#vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index f2340e9c0b3396191ab668270c2b03239dae0973..b261fdd280e2ea5bcfc866dfa8b35250bcb56ffe 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index 6cff9fd980fabad075b1f9b189a6cc18ee680546..b36839e7c83697574b720f848e19297be32b82d3 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_180 ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
- set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index f37749c422e32c23f900ed357a53554405a8294e..049a6ef228e39ed326022ff1f0d3a95b892dd12f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 2b12ee54636a8be29c114ecce7ad906af56f3f2a..45e98a1c47c1cdb750252cbc8127c4b8c522e99b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index bdfae1a527ec7360a9b635fadaad450739db397a..f881b77a856ecf14cdd998a97aeb7f399009c6a1 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 53a802adb6f922eec4493a399ba2b15520732403..bb05a34afe0f020702ca784f11baa36adb2ed9a8 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index b66ce87ea766c71e152a06af1aa5a8e4ab02839f..1650d44f51fa3f3044d92b4f95ef255c00257cbf 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 071b89b37c141a229d86cf908135def66a7ce972..1394d1d34b471707e8a33267468f54f99bd6207a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index e3f92714a83dcba04450a80ee38d3241bf2d002a..8b021c649079174643f4865f00e51914a5d9c997 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index a8eaa493ac3393b0bbebdb602f4899e53c37fb39..2cfbbd059dcf6e3019c3a096a5a80134b437337d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index b8807be1cbac9e867a056e1109fc3b78eb58830b..63035b8e07cf7d4c2fab84dd72af2a901f992a48 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index c56d4e91ac0ae8415517841e40cfc662afa4abe5..d7825e3efccb1b18a4fbc75e91125692ee7ddfd1 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 73fa6f8f5cb184d7c358a03796294b5ce0f29bbe..2638a04129dcefb3efba4a0a34592ae7cba6381d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 1c94289e4d03d0cd87864442dcd74619393057bb..e1a1ada8b9df39c2a88790b9e7c2107a134d0cdf 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index a85380c61312ffdadf6d576ef01e280872adccea..35a821a428baccf96d358096efd150f4fe3a0099 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 2e7823626a535a6f2706e337d5d3c32e2fd9ae8d..a708e8034288473042353c0399da5b1e911d2580 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index c24a4453fb09031527b604d89d7475d075b3e972..cb20b751c9200f10605bc6a094fcf85c1741da75 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 3e676ef14e722598489a37a607136cdc4dcdaa49..1f003afd9b87762c816f1489a7b13e2a25cbca59 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index d2d006e2d481e00f05910e4dfc475332b3b93f42..88fb5e8af9c9b49f57f739f9f1582b281ca95fa2 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 0e5423362c380d4ccbb445b10987a6d13f6ae7c2..f93c3aa93962977cf4ee463ef6f74334ac921081 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 34c167c2497a22c7007173ad80330ed6b4206e69..0c3631101ad1539dbe263e445c8b1fcd5246f675 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 905108fd60f8a981c997c71d2c59e22041661706..7d453434694e4580eae0dce1ddcac777a90d8d72 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index c56852378e4dcf2d109222a790d47ed0c9e1d2a8..aecf94dba75fa49f6bfd0abaa96016f08bcea4d1 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index f7ef50002f70065e1d834ead6bea36d2dcc8c917..1c211f6ce77eab1736f2cdb2293dc4304b866453 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 08af64258001803ea9686b948edbfdc10803a66c..8baf093d8acfa333d161d9bb74c5255017caa205 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index cc872305e161b0cf98793f58b1e12a667709a0f1..8d098b26ceb1370b059ca79aa43962b836ce3e2e 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
vmap altera_mult_add_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index fbbe1b65ff3129a58295dd3a7f56cbda22d61e09..ea8fcb393b6adc0ff7a367cbc523904718395e74 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index dc2b3c96ca25f18a7841942c2dad42e4f328bfd1..4914557dcbf6e8011aaaabd48f793397caf55446 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index f607c01d581180894d6286da324a0147a7eb2001..2736172286780eef136f59560c695e36175ecae3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 132cf13a39329e6285987fed19743f4ffabcf3b7..ba97097939ca4de7b4a7a139c604614f9f2b37eb 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 0cce3fc118b064405f3fc2f237c2b4a02a45b4b3..94616624b526848a0e4b0c8717d4689323dc6a03 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 932f302d9d96624112fafbc1e7dc83ce92c495a2..6a653bed8e598ff98f9d053f348709a2ff126639 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 3ec7a3f76d6c860faae85bf5ac5a382fcb0a91dc..3a060c4715c7aba668425aa5038bd97499e30e4f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 8b564fb73544411f119b7e2e0e34cf1b81844e11..f63bb14398415de260495a90bd9aa70900ea1aed 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 16c61f7f28d85da50a849bec60e5bf8d761d2b25..31257d769e70a8d1dd370da0c2fa8117d34d8af6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index e26265c54cd9a986be536c0949dcd2143349d98c..615c1c48fa0d844ea7845145659dfdf8ca3b48e1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 08c36c7e6bcc2a280e0dcba3453d8ba55f3654a9..1343afc3b59a5e9269152b2004812ae90625603b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 5c0565879faeac0947fed6c7571e4103242fca50..39e0cd631e72644f1d203e6246b3e77b332265e8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index abcdbf22cc16c47fcadfc702ea2e9482c9095a73..d18342e3f5b6c088b1bf6e2fd5d7c3c7c8052276 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index b9156b864897ed9d78b03580ed0fd2b0fe7463e5..1770bb5f7782fc68ff8f718df218d3203306034a 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index 629cba7f7a4e8cec7f9c2a37dc9ae7898bcb7c1d..edfbbf4c076bd1b13d4585581613c7852b6f8a5c 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 68c9111689a661c1e9b5a928a5f32bd955efc0eb..be6b835b4b71ca53fe0866975eafc68a02e34b81 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 7368bf10991125a08073858188d8e74eb31bfa22..40eb599bd5eeca7d2b25ad20a2ecbd476ff9b671 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index a91bebfc952e54d693b1279867e91e545a756d12..d270a6265bc624ef99883794931b78f88e83bd5b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index b5719ceac4d032ff9c92abcb5cb3216bd8c19634..054104dc07c3b24b524a7788406455f2a9fb01f3 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index ea142b01622532d6cb79ed852ebedf97fb158b56..141472385b783d24ddbaeec56d95475194a95e27 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 3511f9a0ed21b8660e4f4b2da5c4adfbaa66273d..f8fb076632d1d86a5d74b02e2955fba283668de2 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
vmap altera_temp_sense_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 3a8ba97963858f302a0dc8f46c81cdbf77771892..dc7c730a2a04dd8aeceebf329166991f094349d7 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index f617a12f5d9d209864d412bd664683c5c9a82b4d..e62b1ca32fe1b8a4193c2430560173f2a1683a2b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 6329d7b22f54e43a657e947c681bdddac1fbebcf..dd46f8828c49145ff271bd4e5b14337efc84f590 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index ba94e344a2ca081d030668981ecf969b07b1727c..11105df2aa676cf5ba385c58df0d9d1baaf61c13 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 60010795b023c1a122b3d5e90ec47dd1b340e4c1..845503837a5dfe9426d87ab1bb73b5b783452931 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index fd5a7bc7719f94555af255293aff785d34418539..a708530bf8c518ffe2fde52eb1429107c1e0e8bc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index aa73121a3ee10b311f75cabfba33af3301b33850..773136b36096cea98d84092d774e3d25c1db2664 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 0ad509c4025e59ea36f83da13c80677d38d06345..87293d4a5f12876019d2b7d5d54a5d096f152139 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index d3794145930c67bd250f2f82c12375a1f68ca3c8..701ee178494a83be2a135ec4af244aacdfcae21e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index 0833cb18e8f07bb5152068ce939d05aba2378e06..a1f71285b5e64a3f00788fa4c6b41d89ff31c8bb 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 8fa8802924a08a317941e21f0f36d3932a5e2b7e..cd49f3f7c3dd6915594bd1429e64fc2644586c81 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index 836cee4bf3453795b5a61e6bce19b02c9a815dc4..d8cfa66c847d5e9da0d6eb5ed42b1ed9796760f3 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index bdd12be22408232f0669599bac4485ea440656f2..665debaad2883da7b3bdea3b76a9e8fdf91a87d6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 383a8782680eab7d6254a00963132ca681559e02..cf074f0e1289216d80eb041de92b8aa70362d851 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index d49c7f2bd1e2ad1d0aac544eb528015ded4a0e35..50f05c573ab1ddd8830edecdb15ff1edaeaf32e1 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 94f8d367a2eb08ffba6af223ef99ba13f607cbba..33ff4e89d52bf16f33c80575ded3d2fa8b12e1ca 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 3e605c0391cb56c3aa26e987ec4db1d5371d2452..407be614316506e93eb94c72fc9431b08a1adbea 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 1fc77affb68809f428646014ab2513854bcc38cb..bb52a542f9bafa95f952930ec469aad1dd88f17f 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index faaf0e7c04dac38ce875cf364921dd7e105bde6f..f4641c545e4a779fd590c6e3a595b3222c5af0cb 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index c8e891987bb324caeb48769adbd1055678e9d4ad..0d545f56085d38f564ecf515fb55d4b47b39aab2 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 1c29d76bf22a8c1da8d0c2cc9e91999fa9244a87..31f2ef1a72c10398288456b6229f87847570601a 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -17,7 +17,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/technology_select_pkg_unb2c.vhd b/libraries/technology/technology_select_pkg_unb2c.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c917c75addffbec503cff882baed27ca9a3c529b
--- /dev/null
+++ b/libraries/technology/technology_select_pkg_unb2c.vhd
@@ -0,0 +1,38 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Define default technology selection value for g_technology.
+-- Description:
+-- In case g_technology is not overruled by the application design then the
+-- g_technology defaults to c_tech_select_default.
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.technology_pkg.ALL;
+
+PACKAGE technology_select_pkg IS
+
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+ --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e3sge3;
+ CONSTANT c_tech_select_default : INTEGER := c_tech_arria10_e1sg;
+
+END technology_select_pkg;