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Commit 9c0da29a authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added mesh terminals: 

 .This is just a dumb instance, for sysnthesis result analysis only!
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applications/apertif/designs/apertif_unb1_correlator/quartus/apertif_unb1_correlator_pins.tcl
+ 1
− 1
View file @ 9c0da29a
...@@ -24,4 +24,4 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc ...@@ -24,4 +24,4 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs.tcl source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_mesh_nocmu_pins.tcl
applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+ 183
− 21
View file @ 9c0da29a
...@@ -42,6 +42,17 @@ USE apertif_lib.apertif_udp_offload_pkg.ALL; ...@@ -42,6 +42,17 @@ USE apertif_lib.apertif_udp_offload_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL; USE wpfb_lib.wpfb_pkg.ALL;
USE bf_lib.bf_pkg.ALL; USE bf_lib.bf_pkg.ALL;
-- Purpose:
--
-- Description:
--
-- Remarks:
-- . Compile times:
-- . 48 Visibility system with dumb terminals : ??? hours, Non-functional design, for resource util exploration only.
-- . 48 Visibility system: : 5.5 hours, fMax ~200MHz, should be functional but it is not.
-- . 48 Visibility system, no DSP : 3.5 hours
-- . 48 Visibility system, BG+offload only : 20 minutes, for visibility offload testing only
ENTITY apertif_unb1_correlator IS ENTITY apertif_unb1_correlator IS
GENERIC ( GENERIC (
g_design_name : STRING := "apertif_unb1_correlator"; g_design_name : STRING := "apertif_unb1_correlator";
...@@ -51,6 +62,7 @@ ENTITY apertif_unb1_correlator IS ...@@ -51,6 +62,7 @@ ENTITY apertif_unb1_correlator IS
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_use_dumb_mesh_terminals : BOOLEAN := TRUE; -- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
g_offload_bg : BOOLEAN := FALSE;-- Bypass everything; use only a block-gen->dp_offload_tx. g_offload_bg : BOOLEAN := FALSE;-- Bypass everything; use only a block-gen->dp_offload_tx.
g_no_dsp : BOOLEAN := FALSE -- True = bypass WPFB, bypass correlator multipliers+accumulators. g_no_dsp : BOOLEAN := FALSE -- True = bypass WPFB, bypass correlator multipliers+accumulators.
); -- . Correlator does output correctly sized DP packets. ); -- . Correlator does output correctly sized DP packets.
...@@ -78,8 +90,19 @@ ENTITY apertif_unb1_correlator IS ...@@ -78,8 +90,19 @@ ENTITY apertif_unb1_correlator IS
-- Transceiver clocks -- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
SB_CLK : IN STD_LOGIC; -- TR clock FN-BN (tr_mesh)
-- Mesh Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-- Serial I/O -- Serial I/O: 10GbE receivers
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
...@@ -298,6 +321,8 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -298,6 +321,8 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0); SIGNAL dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams+1+1-1 DOWNTO 0);
-- De and Reinterleaver -- De and Reinterleaver
SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
SIGNAL dp_pipeline_snk_in : t_dp_sosi;
SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0); SIGNAL interleaved_arr : t_dp_sosi_arr(c_nof_10GbE_streams*c_nof_bf_modules-1 DOWNTO 0);
SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0); SIGNAL deinterleaved_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0); SIGNAL reinterleave_in_arr : t_dp_sosi_arr(c_nof_inputs-1 DOWNTO 0);
...@@ -316,6 +341,16 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -316,6 +341,16 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL apertif_unb1_correlator_vis_offload_snk_out : t_dp_siso; SIGNAL apertif_unb1_correlator_vis_offload_snk_out : t_dp_siso;
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0); SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(1-1 DOWNTO 0); SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(1-1 DOWNTO 0);
-- Mesh terminals
SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
SIGNAL mesh_tx_snk_out_2arr : t_unb1_board_mesh_siso_2arr;
SIGNAL mesh_tx_snk_in_2arr : t_unb1_board_mesh_sosi_2arr;
SIGNAL mesh_rx_src_in_2arr : t_unb1_board_mesh_siso_2arr;
SIGNAL mesh_rx_src_out_2arr : t_unb1_board_mesh_sosi_2arr;
BEGIN BEGIN
gen_no_offload_bg: IF g_offload_bg=FALSE GENERATE gen_no_offload_bg: IF g_offload_bg=FALSE GENERATE
...@@ -544,22 +579,11 @@ BEGIN ...@@ -544,22 +579,11 @@ BEGIN
END GENERATE; END GENERATE;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- RX: 3 BSN monitors for the 3 incoming streams -- RX: BSN monitors at several stages in the stream
-- +1 BSN monitor for post-BSN aligner stream(0)
-- +1 BSN monitor for correlator output
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
dp_bsn_monitor_in_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) <= dp_offload_rx_src_in_arr;
dp_bsn_monitor_in_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) <= dp_offload_rx_restored_src_out_arr;
-- Use the 4th BSN monitor instance to monitor post-BSN aligner stream(0)
dp_bsn_monitor_in_sosi_arr(c_nof_10GbE_streams) <= dp_bsn_align_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(c_nof_10GbE_streams) <= dp_bsn_align_src_in_arr(0);
-- Use the 5th BSN monitor instance to monitor the correlator output
dp_bsn_monitor_in_sosi_arr(c_nof_10GbE_streams+1) <= correlator_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(c_nof_10GbE_streams+1) <= c_dp_siso_rdy;
u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP ( GENERIC MAP (
g_nof_streams => c_nof_10GbE_streams+1+1, g_nof_streams => 5,
g_log_first_bsn => TRUE g_log_first_bsn => TRUE
) )
PORT MAP ( PORT MAP (
...@@ -574,11 +598,27 @@ BEGIN ...@@ -574,11 +598,27 @@ BEGIN
in_sosi_arr => dp_bsn_monitor_in_sosi_arr in_sosi_arr => dp_bsn_monitor_in_sosi_arr
); );
-- 0) Monitor the BSN-aligned output
dp_bsn_monitor_in_sosi_arr(0) <= dp_bsn_align_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(0) <= dp_bsn_align_src_in_arr(0);
-- 1) Monitor the rewired/reinterleaver stage output / WPFB input
dp_bsn_monitor_in_sosi_arr(1) <= wpfb_snk_in_arr(0);
dp_bsn_monitor_in_siso_arr(1) <= c_dp_siso_rdy;
-- 2) Monitor the WPFB output / correlator input
dp_bsn_monitor_in_sosi_arr(2) <= wpfb_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(2) <= c_dp_siso_rdy;
-- 3) Monitor the correlator output / visibility offload input
dp_bsn_monitor_in_sosi_arr(3) <= correlator_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(3) <= c_dp_siso_rdy;
-- 3) Monitor the correlator output / visibility offload input
dp_bsn_monitor_in_sosi_arr(4) <= dp_offload_tx_src_out_arr(0);
dp_bsn_monitor_in_siso_arr(4) <= dp_offload_tx_src_in_arr(0);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0: -- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0:
-- . Beamlet indices between parentheses () -- . Beamlet indices between parentheses ()
-- . Stream indices between brackets [] -- . Stream indices between brackets [] /-Insert Mesh terminals here (?) after deinterleaved_arr
-- -- /
-- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23] [23]--(T2,B7)--[1]-reinter-[11]--(T1,B7),(T2,B7)--unfold-[1]--(T2,B7)-->[23] -- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23] [23]--(T2,B7)--[1]-reinter-[11]--(T1,B7),(T2,B7)--unfold-[1]--(T2,B7)-->[23]
-- \[0]--(T2,B6)--[22] [15]--(T1,B7)--[0]/ \[0]--(T1,B7)-->[22] -- \[0]--(T2,B6)--[22] [15]--(T1,B7)--[0]/ \[0]--(T1,B7)-->[22]
-- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21] [07]--(T0,B7)--[1]-reinter-[10]--(T2,B6),(T0,B7)--unfold-[1]--(T0,B7)-->[21] -- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21] [07]--(T0,B7)--[1]-reinter-[10]--(T2,B6),(T0,B7)--unfold-[1]--(T0,B7)-->[21]
...@@ -606,8 +646,12 @@ BEGIN ...@@ -606,8 +646,12 @@ BEGIN
-- ^ ^ ^ ^ ^ -- ^ ^ ^ ^ ^
-- interleaved_arr | reinterleave_in_arr | Unfolded correlator inputs -- interleaved_arr | reinterleave_in_arr | Unfolded correlator inputs
-- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr -- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_deinterleave_snk_in_arr: IF g_use_dumb_mesh_terminals=FALSE GENERATE
dp_pipeline_snk_in <= interleaved_arr(0);
dp_deinterleave_snk_in_arr <= interleaved_arr;
END GENERATE;
gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
u_deinterleave : ENTITY dp_lib.dp_deinterleave u_deinterleave : ENTITY dp_lib.dp_deinterleave
GENERIC MAP ( GENERIC MAP (
...@@ -622,11 +666,11 @@ BEGIN ...@@ -622,11 +666,11 @@ BEGIN
rst => dp_rst, rst => dp_rst,
clk => dp_clk, clk => dp_clk,
snk_in => interleaved_arr(i), snk_in => dp_deinterleave_snk_in_arr(i),
src_out_arr => deinterleaved_arr(2*i+1 DOWNTO 2*i) src_out_arr => deinterleaved_arr(2*i+1 DOWNTO 2*i)
); );
END GENERATE; END GENERATE;
p_reorder_array : PROCESS(deinterleaved_arr) p_reorder_array : PROCESS(deinterleaved_arr)
BEGIN BEGIN
FOR i IN 0 TO 2*c_nof_bf_modules-1 LOOP FOR i IN 0 TO 2*c_nof_bf_modules-1 LOOP
...@@ -664,7 +708,7 @@ BEGIN ...@@ -664,7 +708,7 @@ BEGIN
rst => dp_rst, rst => dp_rst,
clk => dp_clk, clk => dp_clk,
-- ST sink -- ST sink
snk_in => interleaved_arr(0), snk_in => dp_pipeline_snk_in, --interleaved_arr(0),
-- ST source -- ST source
src_out => wpfb_snk_in_ctrl src_out => wpfb_snk_in_ctrl
); );
...@@ -679,6 +723,124 @@ BEGIN ...@@ -679,6 +723,124 @@ BEGIN
END LOOP; END LOOP;
END PROCESS; END PROCESS;
-----------------------------------------------------------------------------
-- Preliminary mesh terminals to explore resource usage of final design:
-- . With g_use_dumb_mesh_terminals=TRUE, the mesh terminals:
-- . Transmit 21/24 beamlets to the other 7 FPGAs via the mesh.
-- . Receive 21/24 beamlets from the other FPGAs via the mesh.
-- . These are DUMB terminals because this will synthesize but not
-- functionally work because the lack of alignment and proper rewiring.
-- . FOR EXPLORATION OF RESOURCE UTILIZATION ONLY!
-----------------------------------------------------------------------------
gen_terminals_mesh : if g_use_dumb_mesh_terminals=TRUE GENERATE
mesh_tx_snk_in_2arr(0)(0) <= interleaved_arr(0);
mesh_tx_snk_in_2arr(0)(1) <= interleaved_arr(1);
mesh_tx_snk_in_2arr(0)(2) <= interleaved_arr(2);
mesh_tx_snk_in_2arr(1)(0) <= interleaved_arr(3);
mesh_tx_snk_in_2arr(1)(1) <= interleaved_arr(4);
mesh_tx_snk_in_2arr(1)(2) <= interleaved_arr(5);
mesh_tx_snk_in_2arr(2)(0) <= interleaved_arr(6);
mesh_tx_snk_in_2arr(2)(1) <= interleaved_arr(7);
mesh_tx_snk_in_2arr(2)(2) <= interleaved_arr(8);
mesh_tx_snk_in_2arr(3)(0) <= interleaved_arr(9);
mesh_tx_snk_in_2arr(3)(1) <= interleaved_arr(10);
mesh_tx_snk_in_2arr(3)(2) <= interleaved_arr(11);
dp_deinterleave_snk_in_arr(0) <= mesh_rx_src_out_2arr(0)(0);
dp_deinterleave_snk_in_arr(1) <= mesh_rx_src_out_2arr(0)(1);
dp_deinterleave_snk_in_arr(2) <= mesh_rx_src_out_2arr(0)(2);
dp_deinterleave_snk_in_arr(3) <= mesh_rx_src_out_2arr(1)(0);
dp_deinterleave_snk_in_arr(4) <= mesh_rx_src_out_2arr(1)(1);
dp_deinterleave_snk_in_arr(5) <= mesh_rx_src_out_2arr(1)(2);
dp_deinterleave_snk_in_arr(6) <= mesh_rx_src_out_2arr(2)(0);
dp_deinterleave_snk_in_arr(7) <= mesh_rx_src_out_2arr(2)(1);
dp_deinterleave_snk_in_arr(8) <= mesh_rx_src_out_2arr(2)(2);
dp_deinterleave_snk_in_arr(9) <= mesh_rx_src_out_2arr(3)(0);
dp_deinterleave_snk_in_arr(10) <= mesh_rx_src_out_2arr(3)(1);
dp_deinterleave_snk_in_arr(11) <= mesh_rx_src_out_2arr(3)(2);
dp_pipeline_snk_in <= mesh_rx_src_out_2arr(0)(0);
u_terminals_mesh : ENTITY unb1_board_lib.unb1_board_terminals_mesh
GENERIC MAP (
g_sim => g_sim,
g_sim_level => 1,
-- System
g_node_type => e_fn,
g_nof_bus => 4,
-- User
g_usr_use_complex => c_use_complex,
g_usr_data_w => 16,
g_usr_frame_len => 176,
g_usr_nof_streams => 4, -- Actually 3 but has to be 4 to prevent errors.
-- Phy
g_phy_nof_serial => 3,
g_phy_gx_mbps => 6250,
g_phy_rx_fifo_size => 176,
g_phy_ena_reorder => TRUE,
-- Tx
g_use_tx => TRUE,
g_tx_input_use_fifo => TRUE,
-- Rx
g_use_rx => TRUE,
g_rx_output_use_fifo => TRUE,
g_rx_output_fifo_size => 176,
g_rx_output_fifo_fill => 0,
g_rx_timeout_w => 0,
-- Monitoring
g_mon_select => 0
)
PORT MAP (
chip_id => ID(2 DOWNTO 0),
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- dp_sync => dp_pps,
tr_clk => SB_clk,
cal_clk => mm_clk,
-- Received beamlets from other nodes
-- rx_usr_siso_2arr => mesh_rx_src_in_2arr,
rx_usr_sosi_2arr => mesh_rx_src_out_2arr,
-- Beamlets transmitted to other nodes
-- tx_usr_siso_2arr => mesh_tx_snk_out_2arr,
tx_usr_sosi_2arr => mesh_tx_snk_in_2arr,
-- Mesh interface level (4 nodes)(4 lanes)
tx_serial_2arr => tx_serial_2arr,
rx_serial_2arr => rx_serial_2arr
-- MM Control
-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
-- reg_diagnostics_mosi => reg_diagnostics_mosi,
-- reg_diagnostics_miso => reg_diagnostics_miso,
-- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
-- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
);
u_unb1_board_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
PORT MAP (
tx_serial_2arr => tx_serial_2arr,
rx_serial_2arr => rx_serial_2arr,
-- Serial I/O
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX
);
END GENERATE;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- WPFB -- WPFB
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
......
applications/apertif/designs/apertif_unb1_correlator/tb/vhdl/tb_apertif_unb1_correlator.vhd
+ 23
− 5
View file @ 9c0da29a
...@@ -73,6 +73,11 @@ ARCHITECTURE tb OF tb_apertif_unb1_correlator IS ...@@ -73,6 +73,11 @@ ARCHITECTURE tb OF tb_apertif_unb1_correlator IS
SIGNAL sens_scl : STD_LOGIC; SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC; SIGNAL sens_sda : STD_LOGIC;
SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL fn_bn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn_bn_1_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn_bn_2_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL fn_bn_3_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
BEGIN BEGIN
...@@ -126,12 +131,25 @@ BEGIN ...@@ -126,12 +131,25 @@ BEGIN
-- Transceiver clocks -- Transceiver clocks
SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
SB_CLK => sa_clk,
-- Serial I/O -- Serial I/O
SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_0_RX => si_fn_0_tx,
SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_1_RX => si_fn_0_tx,
SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_2_RX => si_fn_0_tx,
SI_FN_3_RX => si_fn_0_tx -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_3_RX => si_fn_0_tx,
FN_BN_0_RX => fn_bn_0_tx,
FN_BN_0_TX => fn_bn_0_tx,
FN_BN_1_RX => fn_bn_1_tx,
FN_BN_1_tX => fn_bn_1_tx,
FN_BN_2_RX => fn_bn_2_tx,
FN_BN_2_TX => fn_bn_2_tx,
FN_BN_3_RX => fn_bn_3_tx,
FN_BN_3_TX => fn_bn_3_tx
); );
END tb; END tb;
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