the 'locked' status of the pll clk25 was not properly connected. fixed

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -327,19 +327,10 @@ BEGIN
   PORT MAP (
     arst       => i_xo_rst25,
     clk25      => i_xo_clk25,
-
     c0_clk20   => i_epcs_clk,
-    c0_rst20   => OPEN,
-
     c1_clk50   => i_mm_clk,
-    c1_rst50   => i_mm_rst,
-
     c2_clk100  => OPEN,
-    c2_rst100  => OPEN,
-
     c3_clk125  => OPEN,
-    c3_rst125  => OPEN,
-
     pll_locked => i_mm_locked
   );
 

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd

@@ -42,41 +42,17 @@ ENTITY unb2_board_clk25_pll IS
     clk25       : IN  STD_LOGIC := '0'; -- connect to UniBoard ETH_clk pin (25 MHz)
 
     c0_clk20    : OUT STD_LOGIC;  -- PLL c0
-    c0_rst20    : OUT STD_LOGIC;
-
     c1_clk50    : OUT STD_LOGIC;  -- PLL c1
-    c1_rst50    : OUT STD_LOGIC;
-
     c2_clk100   : OUT STD_LOGIC;  -- PLL c2
-    c2_rst100   : OUT STD_LOGIC;
-
     c3_clk125   : OUT STD_LOGIC;  -- PLL c3
-    c3_rst125   : OUT STD_LOGIC;
-
     pll_locked  : OUT STD_LOGIC
   );
 END unb2_board_clk25_pll;
 
 
 ARCHITECTURE arria10 OF unb2_board_clk25_pll IS
-
-  CONSTANT c_reset_len : NATURAL := c_meta_delay_len;
-
-  SIGNAL i_c0_clk20   : STD_LOGIC;
-  SIGNAL i_c1_clk50   : STD_LOGIC;
-  SIGNAL i_c2_clk100  : STD_LOGIC;
-  SIGNAL i_c3_clk125  : STD_LOGIC;
-  
-  SIGNAL locked       : STD_LOGIC;
-  SIGNAL locked_n     : STD_LOGIC;
-
 BEGIN
 
-  c0_clk20  <= i_c0_clk20;
-  c1_clk50  <= i_c1_clk50;
-  c2_clk100 <= i_c2_clk100;
-  c3_clk125 <= i_c3_clk125;
-    
   u_pll : ENTITY tech_pll_lib.tech_pll_clk25
   GENERIC MAP (
     g_technology => g_technology
@@ -84,59 +60,10 @@ BEGIN
   PORT MAP (
     areset  => arst,
     inclk0  => clk25,
-    c0      => i_c0_clk20,
-    c1      => i_c1_clk50,
-    c2      => i_c2_clk100,
-    c3      => i_c3_clk125,
-    locked  => locked
-  );
-  
-  -- Release clock domain resets after some clock cycles when the PLL has locked  
-  locked_n   <= NOT locked;
-  pll_locked <= locked;
-  
-  u_rst20 : ENTITY common_lib.common_areset
-  GENERIC MAP (
-    g_rst_level => '1',
-    g_delay_len => c_reset_len
-  )
-  PORT MAP (
-    in_rst    => locked_n,
-    clk       => i_c0_clk20,
-    out_rst   => c0_rst20
+    c0      => c0_clk20,
+    c1      => c1_clk50,
+    c2      => c2_clk100,
+    c3      => c3_clk125,
+    locked  => pll_locked
   );
-
-  u_rst50 : ENTITY common_lib.common_areset
-  GENERIC MAP (
-    g_rst_level => '1',
-    g_delay_len => c_reset_len
-  )
-  PORT MAP (
-    in_rst    => locked_n,
-    clk       => i_c1_clk50,
-    out_rst   => c1_rst50
-  );
-  
-  u_rst100 : ENTITY common_lib.common_areset
-  GENERIC MAP (
-    g_rst_level => '1',
-    g_delay_len => c_reset_len
-  )
-  PORT MAP (
-    in_rst    => locked_n,
-    clk       => i_c2_clk100,
-    out_rst   => c2_rst100
-  );
-
-  u_rst125 : ENTITY common_lib.common_areset
-  GENERIC MAP (
-    g_rst_level => '1',
-    g_delay_len => c_reset_len
-  )
-  PORT MAP (
-    in_rst    => locked_n,
-    clk       => i_c3_clk125,
-    out_rst   => c3_rst125
-  );
-  
 END arria10;