Added c_diag_wg_latency to determine inital WG phase.

libraries/base/diag/src/vhdl/diag_pkg.vhd

@@ -88,6 +88,7 @@ PACKAGE diag_pkg IS
   CONSTANT c_diag_wg_freq_unit          : REAL := 2**REAL(c_diag_wg_freq_w);                                       -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
   CONSTANT c_diag_wg_phase_unit         : REAL := 2**REAL(c_diag_wg_phase_w)/ 360.0;                               -- ^= 1 degree
   
+  CONSTANT c_diag_wg_latency            : NATURAL := 10;  -- WG starts 10 cycles after trigger
   CONSTANT c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
                                          TO_UVEC(              1024, c_diag_wg_nofsamples_w),
                                          TO_UVEC(                 0, c_diag_wg_phase_w),