RTSD-93, review comment 3

applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd

@@ -25,7 +25,7 @@ begin
       i_out_dat_y       <= (others => '0');
       out_val           <= '0';
       out_sync          <= '0';
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       -- Inputs.
       -- Outputs.
       i_out_dat_x       <= nxt_out_dat_x;

applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd

@@ -27,7 +27,7 @@ begin
       out_val        <= (others => '0');
       out_sync       <= '0';
       cnt            <= 0;
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       i_out_dat_x    <= nxt_out_dat_x;
       i_out_dat_y    <= nxt_out_dat_y;
       out_val        <= nxt_out_val;

applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd

@@ -107,7 +107,7 @@ begin
       wr_dat   <= (others => '0');
       reg_re   <= (others => '0');
       reg_im   <= (others => '0');
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       init     <= nxt_init;
       cnt      <= nxt_cnt;
       sig      <= nxt_sig;
@@ -323,7 +323,7 @@ begin
   begin
     if rst = '1' then
       fifo_dat <= (others => (others => '0'));
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       fifo_dat <= nxt_fifo_dat;
     end if;
   end process;
@@ -343,7 +343,7 @@ begin
   begin
     if rst = '1' then
       fifo_dat <= (others => (others => '0'));
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       fifo_dat <= nxt_fifo_dat;
     end if;
   end process;

applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd

@@ -156,7 +156,7 @@ begin
       wr_dat   <= (others => '0');
       reg_re   <= (others => '0');
       reg_im   <= (others => '0');
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       init     <= nxt_init;
       cnt      <= nxt_cnt;
       sig      <= nxt_sig;
@@ -372,7 +372,7 @@ begin
   begin
     if rst = '1' then
       fifo_dat <= (others => (others => '0'));
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       fifo_dat <= nxt_fifo_dat;
     end if;
   end process;
@@ -392,7 +392,7 @@ begin
   begin
     if rst = '1' then
       fifo_dat <= (others => (others => '0'));
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       fifo_dat <= nxt_fifo_dat;
     end if;
   end process;

applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd

@@ -78,7 +78,7 @@ begin
       yi_b        <= (others => '0');
       yr_add      <= '0';
       yi_add      <= '0';
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       xr          <= nxt_xr;
       xi          <= nxt_xi;
       pipe_val    <= nxt_pipe_val;

applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd

@@ -127,7 +127,7 @@ begin
       yi_b        <= (others => '0');
       yr_add      <= '0';
       yi_add      <= '0';
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       xr          <= nxt_xr;
       xi          <= nxt_xi;
       pipe_val    <= nxt_pipe_val;

applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd

@@ -94,7 +94,7 @@ begin
       adr         <= (others => '0');
       coeff_re    <= (others => '0');
       coeff_im    <= (others => '0');
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       reg_val     <= nxt_reg_val;
       reg_sync    <= nxt_reg_sync;
       cnt         <= nxt_cnt;

applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd

@@ -121,7 +121,7 @@ begin
       adr         <= (others => '0');
       coeff_re    <= (others => '0');
       coeff_im    <= (others => '0');
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       reg_val     <= nxt_reg_val;
       reg_sync    <= nxt_reg_sync;
       cnt         <= nxt_cnt;

libraries/base/common/src/vhdl/common_init.vhd

@@ -74,7 +74,7 @@ begin
       hold_reg      <= '1';
       init          <= '0';
       init_reg      <= '0';
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       prev_cnt_en   <= cnt_en;
       hold_reg      <= cnt_en;
       hold          <= hold_reg;

libraries/base/common/src/vhdl/common_peak.vhd

@@ -86,7 +86,7 @@ begin
 
   p_regs : process(clk)
   begin
-    if RISING_EDGE(clk) then
+    if rising_edge(clk) then
       r <= rin;
     end if;
   end process;

libraries/base/common/src/vhdl/common_spulse.vhd

@@ -82,7 +82,7 @@ begin
       out_level      <= '0';
       prev_out_level <= '0';
       out_pulse      <= '0';
-    elsif RISING_EDGE(out_clk) then
+    elsif rising_edge(out_clk) then
       if out_clken = '1' then
         meta_level     <= in_level & meta_level(0 to meta_level'high - 1);
         out_level      <= meta_level(meta_level'high);
@@ -97,7 +97,7 @@ begin
     if in_rst = '1' then
       meta_ack  <= (others => '0');
       pulse_ack <= '0';
-    elsif RISING_EDGE(in_clk) then
+    elsif rising_edge(in_clk) then
       if in_clken = '1' then
         meta_ack  <= out_level & meta_ack(0 to meta_ack'high - 1);
         pulse_ack <= meta_ack(meta_ack'high);

libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd

@@ -135,7 +135,7 @@ begin
 
     p_regs : process(dp_clk)
     begin
-      if RISING_EDGE(dp_clk) then
+      if rising_edge(dp_clk) then
         r <= rin;
       end if;
     end process;

libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd

@@ -168,7 +168,7 @@ begin
 
     p_regs : process(dp_clk)
     begin
-      if RISING_EDGE(dp_clk) then
+      if rising_edge(dp_clk) then
         r <= rin;
       end if;
     end process;

libraries/base/dp/src/vhdl/dp_sync_checker.vhd

@@ -166,7 +166,7 @@ begin
 
   p_regs : process(dp_clk)
   begin
-    if RISING_EDGE(dp_clk) then
+    if rising_edge(dp_clk) then
       r <= rin;
     end if;
   end process;

libraries/base/reorder/src/vhdl/reorder_sequencer.vhd

@@ -314,7 +314,7 @@ begin
 
   p_regs : process(dp_clk)
   begin
-    if RISING_EDGE(dp_clk) then
+    if rising_edge(dp_clk) then
       r <= rin;
     end if;
   end process;

libraries/base/sens/src/vhdl/sens_ctrl.vhd

@@ -119,7 +119,7 @@ begin
       evt_val_reg    <= '0';
       evt_dat        <= (others => '0');
       i_evt_dat_reg  <= (others => '0');
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       seq_start      <= nxt_seq_start;
       seq_cnt        <= nxt_seq_cnt;
       clk_cnt        <= nxt_clk_cnt;

libraries/base/tst/src/vhdl/tst_input.vhd

@@ -109,7 +109,7 @@ begin
       gap_count <= 0;
       out_wait  <= '0';
       out_sync  <= '0';
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       state     <= nxt_state;
       rd_dat    <= nxt_rd_dat;
       rd_val    <= nxt_rd_val;

libraries/base/tst/src/vhdl/tst_output.vhd

@@ -54,7 +54,7 @@ begin
     if rst = '1' then
       file_close(out_file);
       file_open (out_file, g_file_name, WRITE_MODE);
-    elsif RISING_EDGE(clk) then
+    elsif rising_edge(clk) then
       if in_val = '1' then
         for i in 0 to g_nof_data - 1 loop
           if g_data_type = "UNSIGNED" then

libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd

@@ -203,7 +203,7 @@ begin
       ram_address     <= (others => '0');
       prv_ram_address <= (others => '0');
       ram_filling     <= '0';
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       ram_address     <= nxt_ram_address;
       prv_ram_address <= ram_address;
       ram_filling     <= nxt_ram_filling;

libraries/dsp/st/src/vhdl/st_histogram.vhd

@@ -292,7 +292,7 @@ begin
   begin
     if dp_rst = '1' then
       snk_in_reg_arr <= (others => c_dp_sosi_rst);
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       snk_in_reg_arr <= nxt_snk_in_reg_arr;
     end if;
   end process;
@@ -310,7 +310,7 @@ begin
   begin
     if dp_rst = '1' then
       prv_ram_pointer    <= '1';
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       prv_ram_pointer    <= ram_pointer;
     end if;
   end process;
@@ -338,7 +338,7 @@ begin
     if dp_rst = '1' then
       prv_bin_reader_mosi        <= c_mem_mosi_rst;
       bin_reader_to_writer_count <= 0;
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       prv_bin_reader_mosi        <= bin_reader_mosi;
       bin_reader_to_writer_count <= nxt_bin_reader_to_writer_count;
     end if;
@@ -366,7 +366,7 @@ begin
   begin
     if dp_rst = '1' then
       bin_writer_mosi     <= c_mem_mosi_rst;
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       bin_writer_mosi     <= nxt_bin_writer_mosi;
     end if;
   end process;
@@ -393,7 +393,7 @@ begin
   begin
     if dp_rst = '1' then
       prv_bin_reader_ram_pointer <= '0';
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       prv_bin_reader_ram_pointer <= bin_reader_ram_pointer;
     end if;
   end process;
@@ -458,7 +458,7 @@ begin
       ram_clear_address <= (others => '0');
       ram_clearing      <= '0';
       data_cnt          <= (others => '0');
-    elsif RISING_EDGE(dp_clk) then
+    elsif rising_edge(dp_clk) then
       ram_clear_address <= nxt_ram_clear_address;
       ram_clearing      <= nxt_ram_clearing;
       data_cnt          <= nxt_data_cnt;