diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
index c6db258b4ac5e4ee327a62a6e44595746288e2d9..2f4d1cce6b99c5dfed081b92cc47a0295abc5e41 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
@@ -25,7 +25,7 @@ begin
i_out_dat_y <= (others => '0');
out_val <= '0';
out_sync <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
-- Inputs.
-- Outputs.
i_out_dat_x <= nxt_out_dat_x;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
index 66e4b0d28b2cdff826d981dc3535be2f0a45cf08..b33201039c075799d66d1c5bb25fd3e3e075a976 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
@@ -27,7 +27,7 @@ begin
out_val <= (others => '0');
out_sync <= '0';
cnt <= 0;
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
i_out_dat_x <= nxt_out_dat_x;
i_out_dat_y <= nxt_out_dat_y;
out_val <= nxt_out_val;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 06c63273cbc090029b37ddbb0e65ce592c5a65a5..5cd8e02ac4b2c6610a83dd7b1571744e98bb24d3 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -107,7 +107,7 @@ begin
wr_dat <= (others => '0');
reg_re <= (others => '0');
reg_im <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
init <= nxt_init;
cnt <= nxt_cnt;
sig <= nxt_sig;
@@ -323,7 +323,7 @@ begin
begin
if rst = '1' then
fifo_dat <= (others => (others => '0'));
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
fifo_dat <= nxt_fifo_dat;
end if;
end process;
@@ -343,7 +343,7 @@ begin
begin
if rst = '1' then
fifo_dat <= (others => (others => '0'));
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
fifo_dat <= nxt_fifo_dat;
end if;
end process;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 0497d8b8564e54c8ca2629f7cd05a557bf1393f9..edbaf8f12ab50be37751245e34690e708d7fa527 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -156,7 +156,7 @@ begin
wr_dat <= (others => '0');
reg_re <= (others => '0');
reg_im <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
init <= nxt_init;
cnt <= nxt_cnt;
sig <= nxt_sig;
@@ -372,7 +372,7 @@ begin
begin
if rst = '1' then
fifo_dat <= (others => (others => '0'));
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
fifo_dat <= nxt_fifo_dat;
end if;
end process;
@@ -392,7 +392,7 @@ begin
begin
if rst = '1' then
fifo_dat <= (others => (others => '0'));
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
fifo_dat <= nxt_fifo_dat;
end if;
end process;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index d98e11253757f3abe0772fd09a2ccd3906fa46c1..b0a1c3b41733a575832f96b018af4f4e474cd537 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -78,7 +78,7 @@ begin
yi_b <= (others => '0');
yr_add <= '0';
yi_add <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
xr <= nxt_xr;
xi <= nxt_xi;
pipe_val <= nxt_pipe_val;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index 707029cf75982f1e32195752f420e6231b4d08ad..77530984b9d175557af59b11e9426031b3c2e6dd 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -127,7 +127,7 @@ begin
yi_b <= (others => '0');
yr_add <= '0';
yi_add <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
xr <= nxt_xr;
xi <= nxt_xi;
pipe_val <= nxt_pipe_val;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index 12136e62db2a9a2b96b500dc9161b55cabcbeb1a..d77f34405f227df3fcc4d86b5a5124459cdc1998 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -94,7 +94,7 @@ begin
adr <= (others => '0');
coeff_re <= (others => '0');
coeff_im <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
reg_val <= nxt_reg_val;
reg_sync <= nxt_reg_sync;
cnt <= nxt_cnt;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index 1d39a8bb5cec316184a50afb3424f40ca86125eb..fbe5a2b8f32fc592cabbae251f682bc4e6340bf5 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -121,7 +121,7 @@ begin
adr <= (others => '0');
coeff_re <= (others => '0');
coeff_im <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
reg_val <= nxt_reg_val;
reg_sync <= nxt_reg_sync;
cnt <= nxt_cnt;
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index d70f9b7e9447d41b897918779775bf0be804fe4e..2028dcae21a181b77f9d141ddd87931500e39798 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -74,7 +74,7 @@ begin
hold_reg <= '1';
init <= '0';
init_reg <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
prev_cnt_en <= cnt_en;
hold_reg <= cnt_en;
hold <= hold_reg;
diff --git a/libraries/base/common/src/vhdl/common_peak.vhd b/libraries/base/common/src/vhdl/common_peak.vhd
index f53e24da4bb1fba6d546cc9a4cf7154a7b3e5619..1765183b3309e4f04cf259822d622939bdac36b4 100644
--- a/libraries/base/common/src/vhdl/common_peak.vhd
+++ b/libraries/base/common/src/vhdl/common_peak.vhd
@@ -86,7 +86,7 @@ begin
p_regs : process(clk)
begin
- if RISING_EDGE(clk) then
+ if rising_edge(clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index 558d6cfdc756692588e125ee9fa3f4831b663fff..61d8e90541d9042d6c527a85c720a6c0e9f4efdb 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -82,7 +82,7 @@ begin
out_level <= '0';
prev_out_level <= '0';
out_pulse <= '0';
- elsif RISING_EDGE(out_clk) then
+ elsif rising_edge(out_clk) then
if out_clken = '1' then
meta_level <= in_level & meta_level(0 to meta_level'high - 1);
out_level <= meta_level(meta_level'high);
@@ -97,7 +97,7 @@ begin
if in_rst = '1' then
meta_ack <= (others => '0');
pulse_ack <= '0';
- elsif RISING_EDGE(in_clk) then
+ elsif rising_edge(in_clk) then
if in_clken = '1' then
meta_ack <= out_level & meta_ack(0 to meta_ack'high - 1);
pulse_ack <= meta_ack(meta_ack'high);
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index be3ba8afb1ddde11b087eae859f6611acc05d28c..4e55f098cd8797e7a806ade3e3de12e81d116932 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -135,7 +135,7 @@ begin
p_regs : process(dp_clk)
begin
- if RISING_EDGE(dp_clk) then
+ if rising_edge(dp_clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index fed5f3f6ef1f03a79d6af35ff45db3f27401f3a9..4a1a1bbd76b90a378d18c69ab57088324f47ab73 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -168,7 +168,7 @@ begin
p_regs : process(dp_clk)
begin
- if RISING_EDGE(dp_clk) then
+ if rising_edge(dp_clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index a8b2f22c93ce6ae55f0b32584a07d548e4e0ff30..bdd968f814f927be864fc260d9a095faf45371bd 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -166,7 +166,7 @@ begin
p_regs : process(dp_clk)
begin
- if RISING_EDGE(dp_clk) then
+ if rising_edge(dp_clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index 179eed53905d4c46f51a0ecf54d5e5a464078a8e..11daf33e8ef6d728129bb4defeb1c6020a04738f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -314,7 +314,7 @@ begin
p_regs : process(dp_clk)
begin
- if RISING_EDGE(dp_clk) then
+ if rising_edge(dp_clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/base/sens/src/vhdl/sens_ctrl.vhd b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
index 080368278a78843918cef619ae9f2ca404659187..cec717fb84d61f2541d004707eac7dd6567db0b2 100644
--- a/libraries/base/sens/src/vhdl/sens_ctrl.vhd
+++ b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
@@ -119,7 +119,7 @@ begin
evt_val_reg <= '0';
evt_dat <= (others => '0');
i_evt_dat_reg <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
seq_start <= nxt_seq_start;
seq_cnt <= nxt_seq_cnt;
clk_cnt <= nxt_clk_cnt;
diff --git a/libraries/base/tst/src/vhdl/tst_input.vhd b/libraries/base/tst/src/vhdl/tst_input.vhd
index 289dbe71fd7edc69e7015ec475c89f846755806e..d56f662cf2eabe64a06c0fc71bbac7378f364c0e 100644
--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd
@@ -109,7 +109,7 @@ begin
gap_count <= 0;
out_wait <= '0';
out_sync <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
state <= nxt_state;
rd_dat <= nxt_rd_dat;
rd_val <= nxt_rd_val;
diff --git a/libraries/base/tst/src/vhdl/tst_output.vhd b/libraries/base/tst/src/vhdl/tst_output.vhd
index 043e2253c5075cf8cffd3f20af6e510d47dbcb58..b4da110cec33e6effb568d0e64eb58b917b5cac1 100644
--- a/libraries/base/tst/src/vhdl/tst_output.vhd
+++ b/libraries/base/tst/src/vhdl/tst_output.vhd
@@ -54,7 +54,7 @@ begin
if rst = '1' then
file_close(out_file);
file_open (out_file, g_file_name, WRITE_MODE);
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
if in_val = '1' then
for i in 0 to g_nof_data - 1 loop
if g_data_type = "UNSIGNED" then
diff --git a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
index 9101b8b270c2769f877763c54b6b2f447b0c8a66..343b1af9e1a4cffc3a094dcabde7a4a28c8a7ffd 100644
--- a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
@@ -203,7 +203,7 @@ begin
ram_address <= (others => '0');
prv_ram_address <= (others => '0');
ram_filling <= '0';
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
ram_address <= nxt_ram_address;
prv_ram_address <= ram_address;
ram_filling <= nxt_ram_filling;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index ad0fbfdacdba78501d470e25b5b16a35752b20de..f078b78e54374223fa6fb33db915d9c052a813e5 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -292,7 +292,7 @@ begin
begin
if dp_rst = '1' then
snk_in_reg_arr <= (others => c_dp_sosi_rst);
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
snk_in_reg_arr <= nxt_snk_in_reg_arr;
end if;
end process;
@@ -310,7 +310,7 @@ begin
begin
if dp_rst = '1' then
prv_ram_pointer <= '1';
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
prv_ram_pointer <= ram_pointer;
end if;
end process;
@@ -338,7 +338,7 @@ begin
if dp_rst = '1' then
prv_bin_reader_mosi <= c_mem_mosi_rst;
bin_reader_to_writer_count <= 0;
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
prv_bin_reader_mosi <= bin_reader_mosi;
bin_reader_to_writer_count <= nxt_bin_reader_to_writer_count;
end if;
@@ -366,7 +366,7 @@ begin
begin
if dp_rst = '1' then
bin_writer_mosi <= c_mem_mosi_rst;
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
bin_writer_mosi <= nxt_bin_writer_mosi;
end if;
end process;
@@ -393,7 +393,7 @@ begin
begin
if dp_rst = '1' then
prv_bin_reader_ram_pointer <= '0';
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
prv_bin_reader_ram_pointer <= bin_reader_ram_pointer;
end if;
end process;
@@ -458,7 +458,7 @@ begin
ram_clear_address <= (others => '0');
ram_clearing <= '0';
data_cnt <= (others => '0');
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
ram_clear_address <= nxt_ram_clear_address;
ram_clearing <= nxt_ram_clearing;
data_cnt <= nxt_data_cnt;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
index d181ebc42ca44fbd4e902a5e74a1aee34d1e04fe..e4b4f4da51cce95a2cff57174d0061c58d7955b3 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
@@ -291,7 +291,7 @@ begin
begin
if mm_rst = '1' then
prv_st_histogram_ram_copi <= c_mem_copi_rst;
- elsif RISING_EDGE(mm_clk) then
+ elsif rising_edge(mm_clk) then
prv_st_histogram_ram_copi <= st_histogram_ram_copi;
end if;
end process;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 2a725e7865963796d8b456a6d7c37b8f318af269..09206c5117db4eddef018969ae23840dd5aeac96 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -231,7 +231,7 @@ begin
begin
if dp_rst = '1' then
stimuli_src_out <= c_dp_sosi_rst;
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
stimuli_src_out <= nxt_stimuli_src_out;
end if;
end process;
@@ -361,7 +361,7 @@ begin
begin
if dp_rst = '1' then
prv_st_histogram_ram_mosi <= c_mem_mosi_rst;
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
prv_st_histogram_ram_mosi <= st_histogram_ram_mosi;
end if;
end process;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
index 6a82f99ee59c662eaf0beec107946c6768bb492d..da861d5828938c17f9eb728d31c5bb39ae115051 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
@@ -228,7 +228,7 @@ begin
p_regs : process(dp_clk)
begin
- if RISING_EDGE(dp_clk) then
+ if rising_edge(dp_clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd b/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd
index 41745c599ce04db8ffdd5891bfe15ebd73c21e5d..1519fdcd353e552effcc5c89a6f12557369d4da6 100644
--- a/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd
+++ b/libraries/io/eth/src/vhdl/eth_checksum_10g.vhd
@@ -69,7 +69,7 @@ begin
if rst = '1' then
sum <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
if cnt_clr = '1' then
sum <= (others => '0');
diff --git a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
index 98947a802c88c7cb0baf5de85c362eb8821471fc..31534bcf36b548d9a547dc42b4c131e3db80738e 100644
--- a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
@@ -105,7 +105,7 @@ begin
prev_smbus_st_idle <= '1';
prev_list_end <= '0';
i_smbus_out_req <= '0';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
i_busy <= nxt_busy;
pend_st_end <= nxt_pend_st_end;
protocol_rd_en <= nxt_protocol_rd_en;
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 2c4fe34b7b2cddda63013cbbccc3f47e4ac57392..2de5cdb2c101a5b912996fd53de9f38346e50323 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -149,7 +149,7 @@ begin
sda_hi <= '1';
sda_lo <= '0';
sda_rx <= '1';
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
clk_cnt <= clk_cnt + 1;
clk_en <= nxt_clk_en;
if clk_en = '1' then
@@ -191,7 +191,7 @@ begin
begin
if streset = '1' or RST = '1' then
start <= '0';
- elsif FALLING_EDGE(sda_rx) then
+ elsif falling_edge(sda_rx) then
if scl_rx = '1' then
start <= '1';
else
@@ -204,7 +204,7 @@ begin
begin
if streset = '1' or RST = '1' then
stop <= '0';
- elsif RISING_EDGE(sda_rx) then
+ elsif rising_edge(sda_rx) then
if scl_rx = '1' then
stop <= '1';
else
@@ -250,7 +250,7 @@ begin
wbytecnt <= 0;
zeroedge_state <= reset;
- elsif RISING_EDGE(scl_rx) then
+ elsif rising_edge(scl_rx) then
-- Latch CTRL register
latch_ctrl_dly <= latch_ctrl;
@@ -342,7 +342,7 @@ begin
end case;
end if;
- elsif FALLING_EDGE(scl_rx) then
+ elsif falling_edge(scl_rx) then
-- Statemachine
-- default assignments (others keep their value accross states during the access)
diff --git a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
index 091b37b8a1f955167d51d613b5679ceca1b3bf43..d661350c4abd169e27c610318cce3d928bad3c7a 100644
--- a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
@@ -90,12 +90,12 @@ begin
-- Support PROTOCOL_WRITE_BYTE
p_write : process (enable, wr_val) -- first write byte is treated as command
begin
- if RISING_EDGE(enable) then
+ if rising_edge(enable) then
cmd_en <= '1';
- elsif FALLING_EDGE(enable) then
+ elsif falling_edge(enable) then
cmd_en <= '0';
end if;
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
cmd_en <= '0';
if cmd_en = '1' then
cmd <= wr_dat;
@@ -111,7 +111,7 @@ begin
-- Support PROTOCOL_READ_BYTE
p_read : process (rd_req)
begin
- if RISING_EDGE(rd_req) then
+ if rising_edge(rd_req) then
case to_integer(unsigned(cmd)) is -- only model read I and V
when LTC4260_CMD_CONTROL => rd_dat <= control_reg;
when LTC4260_CMD_ALERT => rd_dat <= (others => '1');
diff --git a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
index 5a58c82bb4fbbcfaff14b059671b9931c8f00d19..2b75d0527bcbb0b1589a872550c21801d15f16f9 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
@@ -77,12 +77,12 @@ begin
p_write : process (enable, wr_val) -- first write byte is treated as command
begin
- if RISING_EDGE(enable) then
+ if rising_edge(enable) then
cmd_en <= '1';
- elsif FALLING_EDGE(enable) then
+ elsif falling_edge(enable) then
cmd_en <= '0';
end if;
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
cmd_en <= '0';
if cmd_en = '1' then
cmd <= to_integer(unsigned(wr_dat));
@@ -99,7 +99,7 @@ begin
p_read : process (rd_req)
begin
- if RISING_EDGE(rd_req) then
+ if rising_edge(rd_req) then
case cmd is -- only model some read cmd
when MAX1617_CMD_READ_REMOTE_TEMP => rd_dat <= std_logic_vector(to_signed(temp,8));
when MAX1617_CMD_READ_CONFIG => rd_dat <= config_reg;
diff --git a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
index 962406cc5851c880aa3f4d7f85537b8e41cc22d2..859c95f5c9516cf60e6668e7807fb5d189b94bbb 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
@@ -79,12 +79,12 @@ begin
p_write : process (enable, wr_val) -- first write byte is treated as command
begin
- if RISING_EDGE(enable) then
+ if rising_edge(enable) then
cmd_en <= '1';
- elsif FALLING_EDGE(enable) then
+ elsif falling_edge(enable) then
cmd_en <= '0';
end if;
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
cmd_en <= '0';
if cmd_en = '1' then
cmd <= wr_dat;
@@ -99,7 +99,7 @@ begin
p_read : process (rd_req)
begin
- if RISING_EDGE(rd_req) then
+ if rising_edge(rd_req) then
case cmd is -- only model read V and read temp
when c_cmd_read_2v5 => rd_dat <= std_logic_vector(to_unsigned(volt_2v5,8));
when c_cmd_read_12v => rd_dat <= std_logic_vector(to_unsigned(volt_12v,8));
diff --git a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
index 3677520eb048d4aff3f68faa480902312f6cef20..f01d48ca017358be8672d1eb4be238f1763621cf 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
@@ -90,12 +90,12 @@ begin
-- Similar for reading data from a register.
p_write : process (enable, wr_val)
begin
- if RISING_EDGE(enable) then
+ if rising_edge(enable) then
cmd_en <= '1';
- elsif FALLING_EDGE(enable) then
+ elsif falling_edge(enable) then
cmd_en <= '0';
end if;
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
cmd_en <= '0';
if cmd_en = '1' then
wr_cmd <= to_integer(unsigned(wr_dat));
@@ -117,12 +117,12 @@ begin
p_read : process (wr_val, rd_req)
begin
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
if cmd_en = '1' then
rd_cmd <= to_integer(unsigned(wr_dat));
end if;
end if;
- if RISING_EDGE(rd_req) then
+ if rising_edge(rd_req) then
case rd_cmd is
when c_cmd_input_0 => rd_dat <= input_reg0; rd_cmd <= c_cmd_input_1;
when c_cmd_input_1 => rd_dat <= input_reg1; rd_cmd <= c_cmd_input_0;
diff --git a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
index 13dd41f952137e23f99ec591a2d84b0dd6138f14..37c8bed78756256dc5a141a3d6031db3d6e817e2 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
@@ -79,12 +79,12 @@ begin
p_write : process (enable, wr_val) -- first write byte is treated as command
begin
- if RISING_EDGE(enable) then
+ if rising_edge(enable) then
cmd_en <= '1';
- elsif FALLING_EDGE(enable) then
+ elsif falling_edge(enable) then
cmd_en <= '0';
end if;
- if RISING_EDGE(wr_val) then
+ if rising_edge(wr_val) then
cmd_en <= '0';
if cmd_en = '1' then
cmd <= to_integer(unsigned(wr_dat));
@@ -98,7 +98,7 @@ begin
p_read : process (rd_req)
begin
- if RISING_EDGE(rd_req) then
+ if rising_edge(rd_req) then
case cmd is -- only model some read cmd
when PMBUS_REG_READ_VOUT_MODE => rd_dat <= std_logic_vector(to_signed(vout_mode,8));
when PMBUS_REG_READ_VIN => rd_dat <= std_logic_vector(to_signed(vin,8));
diff --git a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
index 222086ff11de1d848a77871164c8071eec8f344d..3074b1afc02788190e169ead838834e79e52a4e6 100644
--- a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
+++ b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
@@ -107,7 +107,7 @@ begin
p_start : process (start)
begin
rs <= start;
- if RISING_EDGE(start) then
+ if rising_edge(start) then
rs <= not stop;
end if;
end process;
@@ -115,7 +115,7 @@ begin
rd_first <= rw and not prev_rw;
p_dev_read : process(SCL)
begin
- if RISING_EDGE(SCL) then
+ if rising_edge(SCL) then
prev_rw <= rw;
end if;
end process;
@@ -124,23 +124,23 @@ begin
begin
case dev_state is
when ST_IDLE =>
- if RISING_EDGE(am) then
+ if rising_edge(am) then
dev_state <= ST_CMD_OR_DATA; -- address match so expect cmd or data
end if;
when ST_CMD_OR_DATA =>
- if RISING_EDGE(stop) then
+ if rising_edge(stop) then
dev_state <= ST_IDLE; -- end of direct data access (write with or without cmd, or read without cmd)
- elsif FALLING_EDGE(rs) then
+ elsif falling_edge(rs) then
dev_state <= ST_READ_CMD; -- read cmd so continue with address
end if;
when ST_READ_CMD =>
- if RISING_EDGE(am) then
+ if rising_edge(am) then
dev_state <= ST_READ_DATA; -- address match so continue with read data
- elsif RISING_EDGE(stop) then
+ elsif rising_edge(stop) then
dev_state <= ST_IDLE; -- no address match occured
end if;
when ST_READ_DATA =>
- if RISING_EDGE(stop) then
+ if rising_edge(stop) then
dev_state <= ST_IDLE; -- end of cmd read data access
end if;
end case;
@@ -162,7 +162,7 @@ begin
process(SDA,SCL,streset,RST)
begin
- if FALLING_EDGE(SDA) then
+ if falling_edge(SDA) then
if strong(SCL) = '1' then
start <= '1';
else
@@ -180,7 +180,7 @@ begin
process(SDA,SCL,streset,RST)
begin
- if RISING_EDGE(SDA) then
+ if rising_edge(SDA) then
if strong(SCL) = '1' then
stop <= '1';
else
@@ -223,7 +223,7 @@ begin
zeroedge_state <= reset;
rd_next <= '0';
- elsif RISING_EDGE(SCL) then
+ elsif rising_edge(SCL) then
-- Latch CTRL register
latch_ctrl_dly <= latch_ctrl;
@@ -317,7 +317,7 @@ begin
end case;
end if;
- elsif FALLING_EDGE(SCL) then
+ elsif falling_edge(SCL) then
-- Statemachine
-- default assignments (others keep their value accross states during the access)
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
index 6d32454ba9f54e59b8f23d4921afd04333e8e75b..1584384970cd2319ae29e970e76e516c326057e0 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
@@ -112,7 +112,7 @@ begin
trigger <= false;
pps_cnt <= 0;
dp_field_blk_snk_in <= c_dp_sosi_rst;
- elsif RISING_EDGE(dp_clk) then
+ elsif rising_edge(dp_clk) then
-- Use signal to indicate if ARP can be enabled.
valid_sha <= vector_or(arp_sha);
valid_spa <= vector_or(arp_spa);
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
index ecf0dcccd78c6a430a2f3597a8bcf6b8e4adbe74..0d57d18c18b901ec6c296e7929e5925f15e28310 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
@@ -197,7 +197,7 @@ begin
-- Sequential process
p_regs : process(clk)
begin
- if RISING_EDGE(clk) then
+ if rising_edge(clk) then
r <= rin;
end if;
end process;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
index f6cd40b2bc5348e2e7761b200ff3e0f5b711eaa2..3fd06e13ed327ea4b428da22bbc667c4593b6cb9 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
@@ -131,7 +131,7 @@ begin
p_packets : process(clk)
begin
- if RISING_EDGE(clk) then
+ if rising_edge(clk) then
ping_dp_field_blk_snk_in.data(c_ping_packet_len - 1 downto 0 ) <= c_ping_packet_slv;
ping_dp_field_blk_snk_in.valid <= ping_dp_field_blk_snk_out.ready;
@@ -149,7 +149,7 @@ begin
p_stimuli : process(clk)
variable start : boolean := false;
begin
- if RISING_EDGE(clk) then
+ if rising_edge(clk) then
if cnt = 5 then
nw_ping_response_snk_in.valid <= '0';
nw_ping_response_snk_in.sop <= '0';
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
index 8cf38ec5a6588584bbf2f50a33f484d2b3f8abb6..1b485b10e3a864278bebf79e69e8e2cbab0732aa 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
@@ -69,7 +69,7 @@ begin
if rst = '1' then
sum <= (others => '0');
- elsif RISING_EDGE(clk) then
+ elsif rising_edge(clk) then
if cnt_clr = '1' then
sum <= (others => '0');