diff --git a/hdl_user_components.ipx b/hdl_user_components.ipx
index e40f426f6a5f69288a1bd3154f3e3ff7f371af1a..4823cbc15af5e791566def51860e88e74611825d 100644
--- a/hdl_user_components.ipx
+++ b/hdl_user_components.ipx
@@ -7,5 +7,4 @@
  <!--  -->
  <!-- D:/svnroot/Uniboard/9.0 -->
  <path path="$RADIOHDL_WORK/libraries/**/*" />
- <path path="$HDL_BUILD_DIR/**/*" />
 </library>
diff --git a/init_hdl.sh b/init_hdl.sh
index eb79078f8124b57a18ccba450281f43eb60a3fcb..9a5ec73efd852f21c910e6d5fcd0719591e8c5e2 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -47,7 +47,7 @@ echo "HDL environment will be setup for" $RADIOHDL_WORK
 user_components_file="${ALTERA_DIR}/user_components.ipx"
 if [ -e $user_components_file ]; then
   echo "removing existing user_components.ipx symbolic link"
-  rm $user_components_file
+  rm -f $user_components_file
 fi
 # make a new symbolic link to the git version
 echo "making a new symbolic link"
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index a4bfba0a13ff5a15840dae36aabe10daa6e0ed53..a7600bb30b0f2ac6f0072a7013780151f34e9079 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -21,18 +21,18 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
 
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index b55e51bdde3ac19be82aeaed23ccc28841919859..621bc2a7c2460b59a06a47da2cc5fac0a32d96e5 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
 LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
 
 ENTITY tech_clkbuf IS
   GENERIC (
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 6564425f2d010587da68966283742e348998e239..7f86edd95ac1fa3df17df07281a54373525a900b 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -34,10 +34,10 @@
 --   DDR interface monitoring purposes.
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180;
 
 LIBRARY IEEE, technology_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index 8ab92809687d21a2bba519305093e5047a4aa7f8..a546364ef186e3b588e1b9e605a909d6f61b772b 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
 LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
---LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
+--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index f0949faec28f99afecb7931899a7d0a00c90d2af..8c54bb8882de34ac5f1ed5d1be9dbd2f57396f88 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_remote_update_altera_remote_update_150;
 LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 65a773084abd2ad7ec2b9e97d690833afc61257b..749310fa3d6bb0ad3dc51d1aaa1abd880551d96c 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
 LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
 
 
 ENTITY tech_fpga_temp_sens IS
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index bc66f172fd61c55364e1fe5cd3afb81c71fdfb9c..f16657aba07348b85c295e2878517ff53c47ca47 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
 LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
 
 
 ENTITY tech_fpga_voltage_sens IS
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index cc8f297c07540396431186aace896b4dfc7b2e3f..287a6098d48ea5d2e847716cca7f7592a8824161 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_fractional_pll_clk125 IS
   GENERIC (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index f30733508e9b2efd2d487f614532c410eb9f9dc4..4a986c4c47ed2d40b2cafb367bbeaa372e76a45e 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_fractional_pll_clk200 IS
   GENERIC (
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index c41aa2774891bb77962b62ea95583f0aadd33648..2acea7c3c25f19121043b8f93f1cab9106542cb6 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_180;
 
 LIBRARY IEEE, technology_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 82975e83418293f02b81b5045c8d1ccaa57fbe09..6432cf385e36cf90f7a7ee7e4911b6f6d039261f 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -31,7 +31,7 @@ LIBRARY ip_stratixiv_mult_lib;
 --LIBRARY ip_arria10_mult_lib;
 --LIBRARY ip_arria10_mult_rtl_lib;
 LIBRARY ip_arria10_complex_mult_altmult_complex_150;
-LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
+LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
 LIBRARY ip_arria10_complex_mult_rtl_lib;
 LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
 
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 5cdbbb6be1a4d276d0f2d45e3f701d4ca56c5bb4..df94261a8337360e01c8283d7079d38e92ef7c3d 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
 
 ENTITY tech_pll_clk125 IS
   GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 4eefc35b6de5375616b1f9bc585a4cc750ba1771..adf88609a918af520b4d93bea13a62c40d831313 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_pll_lib;
 LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
 
 ENTITY tech_pll_clk200 IS
   GENERIC (
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 2521432735ce688387a6fa211a847973d1ef7845..bfb242b469fe81c81b35920dc91ad24acb4aab02 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
 LIBRARY ip_stratixiv_pll_clk25_lib;
 LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
 
 ENTITY tech_pll_clk25 IS
   GENERIC (
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 28f1fa3a1ed8ac9a886605359bd397afc11640ca..ca3990942354cdc18be4a0cd19a240d9ea4239e8 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_pll_xgmii_mac_clocks IS
   GENERIC (
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 4512fe7d9e9a08487caa41b6376ce774ee07ef82..664f3f85ecbc4e6a2d853b9a02bfb9ae635dfc07 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180;
 
 ENTITY tech_tse_arria10_e1sg IS
   GENERIC (