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Commit 9551a1ab authored by Reinier van der Walle's avatar Reinier van der Walle
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......@@ -7,7 +7,7 @@ hdl_lib_technology =
synth_files =
src/vhdl/eth_pkg.vhd
src/vhdl/eth_checksum.vhd
src/vhdl/eth_checksum_10G.vhd
src/vhdl/eth_checksum_10g.vhd
src/vhdl/eth_hdr_store.vhd
src/vhdl/eth_hdr_status.vhd
src/vhdl/eth_hdr_ctrl.vhd
......
......@@ -46,7 +46,7 @@ USE dp_lib.dp_stream_pkg.ALL;
-- snk_in.valid is inactive and that snk_in.valid is only active for new
-- data.
ENTITY eth_checksum_10G_tx IS
ENTITY eth_checksum_10g IS
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
......@@ -57,9 +57,9 @@ ENTITY eth_checksum_10G_tx IS
src_in : IN t_dp_siso;
snk_out : OUT t_dp_siso
);
END eth_checksum_10G_tx;
END eth_checksum_10g;
ARCHITECTURE rtl OF eth_checksum_10G_tx IS
ARCHITECTURE rtl OF eth_checksum_10g IS
CONSTANT c_cin_w : NATURAL := 4; --true_log2(c_nof_half_words - 1);
CONSTANT c_pipeline_delay : NATURAL := 2;
......
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