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libraries/io/eth/hdllib.cfg

@@ -26,7 +26,6 @@ synth_files =
 test_bench_files = 
     src/vhdl/eth_statistics.vhd
     tb/vhdl/tb_eth_checksum.vhd
-    tb/vhdl/tb_eth_checksum_10G.vhd
     tb/vhdl/tb_eth_crc_ctrl.vhd
     tb/vhdl/tb_eth_hdr.vhd
     tb/vhdl/tb_eth.vhd

libraries/io/eth/tb/vhdl/tb_eth_checksum_10G.vhd

--------------------------------------------------------------------------------
---
--- Copyright (C) 2010
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-
--- Purpose: Testbench for eth_checksum
--- Description:
---
---   Example from Wiki IPv4. Use Hex 45000030442240008006442e8c7c19acae241e2b
---   (20Bytes IP header) the c_exp_checksum then becomes:
---
---     4500 + 0030 + 4422 + 4000 + 8006 + 0000 + 8c7c + 19ac + ae24 + 1e2b = 2BBCF
---     2 + BBCF = BBD1 = 1011101111010001, the 1'S of sum = 0100010000101110 = 442E
---
---   Verify that checksum=c_exp_checksum when checksum_val='1'
---
--- Usage:
---   > as 10
---   > run -all
-
-LIBRARY IEEE, common_lib, dp_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE work.eth_pkg.ALL;
-
-
-ENTITY tb_eth_checksum_10G IS
-END tb_eth_checksum_10G;
-
-
-ARCHITECTURE tb OF tb_eth_checksum_10G IS
-
-  CONSTANT clk_period : TIME := 10 ns;  -- 100 MHz
-  
-  CONSTANT c_exp_checksum     : NATURAL := 16#442E#;
-  
-  -- Minimum nof clk cycles between eop and sop
-  CONSTANT c_checksum_latency : NATURAL := 3;
-  CONSTANT c_wait_eop_sop     : NATURAL := 10;  -- >= c_checksum_latency-1;
-
-  SIGNAL tb_end        : STD_LOGIC := '0';
-  SIGNAL clk           : STD_LOGIC := '1';
-  SIGNAL rst           : STD_LOGIC;
-  
-  SIGNAL src_out       : t_dp_sosi;
-  
-  SIGNAL checksum      : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0);
-  SIGNAL checksum_val  : STD_LOGIC;
-    
-BEGIN
-
-  clk <= NOT clk OR tb_end AFTER clk_period/2;
-  rst <= '1', '0' AFTER 3*clk_period;
-  
-  p_stimuli : PROCESS
-  BEGIN
-    src_out.data  <= TO_DP_DATA(0);
-    src_out.valid <= '0';
-    src_out.sop   <= '0';
-    src_out.eop   <= '0';
-    src_out.empty <= TO_DP_EMPTY(0);
-    WAIT UNTIL rst='0';
-    WAIT UNTIL rising_edge(clk);
-    
-    ----------------------------------------------------------------------------
-    -- First
-    ----------------------------------------------------------------------------
-    src_out.sop   <= '1';
-    src_out.valid <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"4500003044224000");
-    WAIT UNTIL rising_edge(clk);
-    src_out.sop   <= '0';
-    src_out.data  <= RESIZE_DP_DATA(X"800600008c7c19ac");
-    WAIT UNTIL rising_edge(clk);
-    src_out.eop   <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"00000000ae241e2b");
-    WAIT UNTIL rising_edge(clk);
-    src_out.data  <= (OTHERS=>'0');
-    src_out.valid <= '0';
-    src_out.eop   <= '0';
-    -- Wait latency    
-    FOR I IN 0 TO c_wait_eop_sop-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    
-    ----------------------------------------------------------------------------
-    -- Again with valid low for a few cycles
-    ----------------------------------------------------------------------------
-    src_out.sop   <= '1';
-    src_out.valid <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"4500003044224000");
-    WAIT UNTIL rising_edge(clk);
-    src_out.sop   <= '0';
-    src_out.data  <= RESIZE_DP_DATA(X"800600008c7c19ac");
-    
-    -- pause
-    src_out.valid <= '0';
-    FOR I IN 0 TO 1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    src_out.valid <= '1';
-    
-    WAIT UNTIL rising_edge(clk);
-    src_out.eop   <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"00000000ae241e2b");
-    WAIT UNTIL rising_edge(clk);
-    src_out.data  <= (OTHERS=>'0');
-    src_out.valid <= '0';
-    src_out.eop   <= '0';
-    -- Wait latency    
-    FOR I IN 0 TO c_wait_eop_sop-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    
-    ----------------------------------------------------------------------------
-    -- Again with carry in within word_sum
-    ----------------------------------------------------------------------------
-    src_out.sop   <= '1';
-    src_out.valid <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"4500003044224000");
---     WAIT UNTIL rising_edge(clk);
---     src_out.data  <= RESIZE_DP_DATA(X"80060000");
---     WAIT UNTIL rising_edge(clk);
---     src_out.data  <= RESIZE_DP_DATA(X"8c7c19ac");
-    WAIT UNTIL rising_edge(clk);
-    src_out.sop   <= '0';
-    src_out.data  <= RESIZE_DP_DATA(X"80068c7c000019ac");
-    
-    -- pause
-    src_out.valid <= '0';
-    FOR I IN 0 TO 0 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    src_out.valid <= '1';
-    
-    WAIT UNTIL rising_edge(clk);
-    src_out.eop   <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"00000000ae241e2b");
-    WAIT UNTIL rising_edge(clk);
-    src_out.data  <= (OTHERS=>'0');
-    src_out.valid <= '0';
-    src_out.eop   <= '0';
-    -- Wait latency    
-    FOR I IN 0 TO c_wait_eop_sop-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    
-    ----------------------------------------------------------------------------
-    -- Again with empty = 2
-    ----------------------------------------------------------------------------
-    src_out.empty <= TO_DP_EMPTY(2);
-    src_out.sop   <= '1';
-    src_out.valid <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"4500003044224000");
-    WAIT UNTIL rising_edge(clk);
-    src_out.sop   <= '0';
-    src_out.data  <= RESIZE_DP_DATA(X"80061e2b8c7c19ac");  -- overwrite these "0000" with the last 2, now empty, bytes "1e2b", to keep the seem expected result
-    WAIT UNTIL rising_edge(clk);
-    src_out.eop   <= '1';
-    src_out.data  <= RESIZE_DP_DATA(X"00000000ae241e2b");
-    WAIT UNTIL rising_edge(clk);
-    src_out.data  <= (OTHERS=>'0');
-    src_out.valid <= '0';
-    src_out.eop   <= '0';
-    -- Wait latency    
-    FOR I IN 0 TO c_wait_eop_sop-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
-    
-    tb_end <= '1';
-    ASSERT FALSE REPORT "Simulation tb_eth_checksum finished." SEVERITY NOTE;
-    WAIT;
-  END PROCESS;
-  
-  
-  p_verify : PROCESS
-  BEGIN
-    WAIT UNTIL rising_edge(clk);
-    IF checksum_val='1' THEN
-      ASSERT UNSIGNED(checksum)=c_exp_checksum REPORT "Wrong checksum" SEVERITY ERROR;
-    END IF;
-    IF tb_end='1' THEN
-      ASSERT checksum_val='1' REPORT "Checksum is not valid at tb_end" SEVERITY ERROR;
-    END IF;
-  END PROCESS;
-  
-  u_dut : ENTITY work.eth_checksum_10G
-  PORT MAP (
-    rst           => rst,
-    clk           => clk,
-    
-    snk_in        => src_out,
-    
-    checksum      => checksum,
-    checksum_val  => checksum_val
-  );
-
-END tb;