From 936908331b83dc3e029b7cb75f55b7f58e2a3059 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Tue, 13 Jan 2015 14:51:47 +0000
Subject: [PATCH] svn copy from unb2_minimal
---
boards/uniboard2/designs/unb2_test/doc/README | 64 +
boards/uniboard2/designs/unb2_test/hdllib.cfg | 38 +
.../unb2_test/quartus/qsys_unb2_test.qsys | 1620 +++++++++++++++++
.../unb2_test/quartus/unb2_test_pins.tcl | 23 +
.../unb2_test/src/vhdl/mmm_unb2_test.vhd | 275 +++
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 136 ++
.../designs/unb2_test/src/vhdl/unb2_test.vhd | 307 ++++
.../unb2_test/tb/python/tc_unb2_test.py | 355 ++++
.../unb2_test/tb/vhdl/tb_unb2_test.vhd | 202 ++
9 files changed, 3020 insertions(+)
create mode 100644 boards/uniboard2/designs/unb2_test/doc/README
create mode 100644 boards/uniboard2/designs/unb2_test/hdllib.cfg
create mode 100644 boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
create mode 100644 boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
create mode 100644 boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
create mode 100644 boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
create mode 100644 boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
create mode 100644 boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
create mode 100644 boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
new file mode 100644
index 0000000000..997d282cf2
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -0,0 +1,64 @@
+Quick steps to compile and use design [unb2_minimal] in RadionHDL
+-----------------------------------------------------------------
+
+
+
+Start with the Oneclick Commands:
+ python $RADIOHDL/tools/oneclick/base/modelsim_config.py -t ip_arria10
+ python $RADIOHDL/tools/oneclick/base/quartus_config.py -t ip_arria10
+
+Generate MMM for QSYS:
+ run_qsys unb2 unb2_minimal
+
+-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
+
+Simulation
+----------
+Modelsim instructions:
+ # in bash do:
+ rm $UNB/Software/python/sim/* # (optional)
+ run_modelsim unb2
+
+ # in Modelsim do:
+ lp unb2_minimal
+ mk all
+ # now double click on testbench file
+ as 10
+ run 500us
+
+ # while the simulation runs... in another bash session do:
+ cd unb2_minimal/tb/python
+ python tc_unb2_minimal.py --sim --unb 0 --bn 3 --seq INFO,PPSH,SENSORS
+
+ # (sensor results only show up after 1000us of simulation runtime)
+
+ # to end simulation in Modelsim do:
+ quit -sim
+
+
+Synthesis
+---------
+Quartus instructions (for QSYS):
+ run_app unb2 unb2_minimal use=gen2
+ run_qcomp unb2 unb2_minimal
+
+In case of needing the Quartus GUI:
+ run_quartus unb2
+
+
+Convert .sof to .rbf:
+ # assuming in /tmp/temp_options_file: Bitstream_compression=on
+ run_rbf unb2 unb2_minimal # QSYS
+
+
+Send to LCU capture5:
+ scp $RADIOHDL/build/quartus/unb2_minimal/unb2_minimal.rbf capture5:~/rbf/ # QSYS
+
+ # Now login on capture5 and use pythonscript to program flash:
+ cd unb2_minimal/tb/python
+
+ # for example use frontnode 0 on uniboard 0:
+ python tc_unb2_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb2_minimal.rbf # QSYS
+
+ python tc_unb2_minimal.py --gn 0 --seq REMU,REGMAP,INFO,PPSH,SENSORS # start design, read info-ppsh-sensors
+
diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
new file mode 100644
index 0000000000..8e7cf84190
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -0,0 +1,38 @@
+hdl_lib_name = unb2_minimal
+hdl_library_clause_name = unb2_minimal_lib
+hdl_lib_uses = common mm unb2_board
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ src/vhdl/qsys_unb2_minimal_pkg.vhd
+ src/vhdl/mmm_unb2_minimal.vhd
+ src/vhdl/unb2_minimal.vhd
+
+test_bench_files =
+ tb/vhdl/tb_unb2_minimal.vhd
+
+synth_top_level_entity =
+
+quartus_copy_files =
+ quartus/qsys_unb2_minimal.qsys .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+
+quartus_tcl_files =
+ quartus/unb2_minimal_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+
+
+# vsim -L ... -L ... ...
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
+
diff --git a/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
new file mode 100644
index 0000000000..2e366698b3
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
@@ -0,0 +1,1620 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "String";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "String";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element cpu_0.debug_mem_slave
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "String";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "392";
+ type = "String";
+ }
+ }
+ element jtag_uart_0.irq
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "String";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "320";
+ type = "String";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "384";
+ type = "String";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "336";
+ type = "String";
+ }
+ }
+ element reg_dpmm_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ }
+ element reg_dpmm_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "376";
+ type = "String";
+ }
+ }
+ element reg_dpmm_data
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ }
+ element reg_dpmm_data.mem
+ {
+ datum baseAddress
+ {
+ value = "368";
+ type = "String";
+ }
+ }
+ element reg_epcs
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ }
+ element reg_epcs.mem
+ {
+ datum baseAddress
+ {
+ value = "192";
+ type = "String";
+ }
+ }
+ element reg_mmdp_ctrl
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ }
+ element reg_mmdp_ctrl.mem
+ {
+ datum baseAddress
+ {
+ value = "360";
+ type = "String";
+ }
+ }
+ element reg_mmdp_data
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element reg_mmdp_data.mem
+ {
+ datum baseAddress
+ {
+ value = "352";
+ type = "String";
+ }
+ }
+ element reg_remu
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element reg_remu.mem
+ {
+ datum baseAddress
+ {
+ value = "224";
+ type = "String";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "String";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "String";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "288";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U3F45I2LG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="unb2_minimal.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="avs_eth_0_clk"
+ internal="avs_eth_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_irq"
+ internal="avs_eth_0.irq"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_address"
+ internal="avs_eth_0.ram_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_read"
+ internal="avs_eth_0.ram_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_write"
+ internal="avs_eth_0.ram_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_address"
+ internal="avs_eth_0.reg_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_read"
+ internal="avs_eth_0.reg_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_write"
+ internal="avs_eth_0.reg_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_reset"
+ internal="avs_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_address"
+ internal="avs_eth_0.tse_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_read"
+ internal="avs_eth_0.tse_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_write"
+ internal="avs_eth_0.tse_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="avs_eth_0_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
+ <interface
+ name="pio_debug_wave_external_connection"
+ internal="pio_debug_wave.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_address"
+ internal="pio_pps.address"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_write"
+ internal="pio_pps.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_address"
+ internal="reg_dpmm_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_clk"
+ internal="reg_dpmm_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_read"
+ internal="reg_dpmm_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_readdata"
+ internal="reg_dpmm_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_reset"
+ internal="reg_dpmm_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_write"
+ internal="reg_dpmm_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_ctrl_writedata"
+ internal="reg_dpmm_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_address"
+ internal="reg_dpmm_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_clk"
+ internal="reg_dpmm_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_read"
+ internal="reg_dpmm_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_readdata"
+ internal="reg_dpmm_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_reset"
+ internal="reg_dpmm_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_write"
+ internal="reg_dpmm_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dpmm_data_writedata"
+ internal="reg_dpmm_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_address"
+ internal="reg_epcs.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_epcs_clk" internal="reg_epcs.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_epcs_read"
+ internal="reg_epcs.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_readdata"
+ internal="reg_epcs.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_reset"
+ internal="reg_epcs.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_write"
+ internal="reg_epcs.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_epcs_writedata"
+ internal="reg_epcs.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_address"
+ internal="reg_mmdp_ctrl.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_clk"
+ internal="reg_mmdp_ctrl.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_read"
+ internal="reg_mmdp_ctrl.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_readdata"
+ internal="reg_mmdp_ctrl.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_reset"
+ internal="reg_mmdp_ctrl.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_write"
+ internal="reg_mmdp_ctrl.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_ctrl_writedata"
+ internal="reg_mmdp_ctrl.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_address"
+ internal="reg_mmdp_data.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_clk"
+ internal="reg_mmdp_data.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_read"
+ internal="reg_mmdp_data.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_readdata"
+ internal="reg_mmdp_data.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_reset"
+ internal="reg_mmdp_data.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_write"
+ internal="reg_mmdp_data.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mmdp_data_writedata"
+ internal="reg_mmdp_data.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_address"
+ internal="reg_remu.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_remu_clk" internal="reg_remu.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_remu_read"
+ internal="reg_remu.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_readdata"
+ internal="reg_remu.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_reset"
+ internal="reg_remu.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_write"
+ internal="reg_remu.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_remu_writedata"
+ internal="reg_remu.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <module name="avs_eth_0" kind="avs2_eth_coe" version="1.0" enabled="1" />
+ <module name="clk_0" kind="clock_source" version="14.1" enabled="1">
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="cpu_0" kind="altera_nios2_gen2" version="14.1" enabled="1">
+ <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
+ <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="bht_ramBlockType" value="Automatic" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="breakSlave" value="None" />
+ <parameter name="cdx_enabled" value="false" />
+ <parameter name="clockFrequency" value="50000000" />
+ <parameter name="cpuArchRev" value="1" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
+ <parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
+ <parameter name="dataAddrWidth" value="18" />
+ <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="dataMasterHighPerformanceMapParam" value="" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='reg_epcs.mem' start='0xC0' end='0xE0' /><slave name='reg_remu.mem' start='0xE0' end='0x100' /><slave name='reg_unb_sens.mem' start='0x100' end='0x120' /><slave name='timer_0.s1' start='0x120' end='0x140' /><slave name='pio_debug_wave.s1' start='0x140' end='0x150' /><slave name='pio_wdi.s1' start='0x150' end='0x160' /><slave name='reg_mmdp_data.mem' start='0x160' end='0x168' /><slave name='reg_mmdp_ctrl.mem' start='0x168' end='0x170' /><slave name='reg_dpmm_data.mem' start='0x170' end='0x178' /><slave name='reg_dpmm_ctrl.mem' start='0x178' end='0x180' /><slave name='pio_pps.mem' start='0x180' end='0x188' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x188' end='0x190' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="data_master_high_performance_paddr_base" value="0" />
+ <parameter name="data_master_high_performance_paddr_size" value="0" />
+ <parameter name="data_master_paddr_base" value="0" />
+ <parameter name="data_master_paddr_size" value="0" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_tagramBlockType" value="Automatic" />
+ <parameter name="dcache_victim_buf_impl" value="ram" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_datatrigger" value="0" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_enabled" value="true" />
+ <parameter name="debug_hwbreakpoint" value="0" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_traceStorage" value="onchip_trace" />
+ <parameter name="debug_traceType" value="none" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="dividerType" value="no_div" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="faAddrWidth" value="1" />
+ <parameter name="faSlaveMapParam" value="" />
+ <parameter name="fa_cache_line" value="2" />
+ <parameter name="fa_cache_linesize" value="0" />
+ <parameter name="flash_instruction_master_paddr_base" value="0" />
+ <parameter name="flash_instruction_master_paddr_size" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_tagramBlockType" value="Automatic" />
+ <parameter name="impl" value="Tiny" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
+ <parameter name="instructionMasterHighPerformanceMapParam" value="" />
+ <parameter name="instruction_master_high_performance_paddr_base" value="0" />
+ <parameter name="instruction_master_high_performance_paddr_size" value="0" />
+ <parameter name="instruction_master_paddr_base" value="0" />
+ <parameter name="instruction_master_paddr_size" value="0" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="io_regionbase" value="0" />
+ <parameter name="io_regionsize" value="0" />
+ <parameter name="master_addr_map" value="false" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="mmu_TLBMissExcSlave" value="None" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="mmu_ramBlockType" value="Automatic" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpx_enabled" value="false" />
+ <parameter name="mul_32_impl" value="2" />
+ <parameter name="mul_64_impl" value="0" />
+ <parameter name="mul_shift_choice" value="0" />
+ <parameter name="ocimem_ramBlockType" value="Automatic" />
+ <parameter name="ocimem_ramInit" value="false" />
+ <parameter name="regfile_ramBlockType" value="Automatic" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateTrace" value="false" />
+ <parameter name="setting_allow_break_inst" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_asic_add_scan_mode_input" value="false" />
+ <parameter name="setting_asic_enabled" value="false" />
+ <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+ <parameter name="setting_asic_third_party_synthesis" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_branchpredictiontype" value="Dynamic" />
+ <parameter name="setting_breakslaveoveride" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_dc_ecc_present" value="true" />
+ <parameter name="setting_disable_tmr_inj" value="false" />
+ <parameter name="setting_disableocitrace" value="false" />
+ <parameter name="setting_dtcm_ecc_present" value="true" />
+ <parameter name="setting_ecc_present" value="false" />
+ <parameter name="setting_ecc_sim_test_ports" value="false" />
+ <parameter name="setting_exportHostDebugPort" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_export_large_RAMs" value="false" />
+ <parameter name="setting_exportdebuginfo" value="false" />
+ <parameter name="setting_exportvectors" value="false" />
+ <parameter name="setting_fast_register_read" value="false" />
+ <parameter name="setting_ic_ecc_present" value="true" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_itcm_ecc_present" value="true" />
+ <parameter name="setting_mmu_ecc_present" value="true" />
+ <parameter name="setting_oci_export_jtag_signals" value="false" />
+ <parameter name="setting_oci_version" value="1" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_removeRAMinit" value="false" />
+ <parameter name="setting_rf_ecc_present" value="true" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_support31bitdcachebypass" value="true" />
+ <parameter name="setting_usedesignware" value="false" />
+ <parameter name="shift_rot_impl" value="1" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
+ <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
+ <parameter name="tmr_enabled" value="false" />
+ <parameter name="tracefilename" value="" />
+ <parameter name="userDefinedSettings" value="" />
+ </module>
+ <module
+ name="jtag_uart_0"
+ kind="altera_avalon_jtag_uart"
+ version="14.1"
+ enabled="1">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="avalonSpec" value="2.0" />
+ <parameter name="clkFreq" value="50000000" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream" value="" />
+ <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ name="onchip_memory2_0"
+ kind="altera_avalon_onchip_memory2"
+ version="14.1"
+ enabled="1">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="AUTO" />
+ <parameter name="copyInitFile" value="false" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceFeatures">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
+ <parameter name="dualPort" value="false" />
+ <parameter name="ecc_enabled" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName">onchip_memory2_0.hex</parameter>
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="resetrequest_enabled" value="true" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ name="pio_debug_wave"
+ kind="altera_avalon_pio"
+ version="14.1"
+ enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module name="pio_pps" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="pio_wdi" kind="altera_avalon_pio" version="14.1" enabled="1">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="50000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module name="reg_dpmm_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_dpmm_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_epcs" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_mmdp_ctrl" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_mmdp_data" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_remu" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_unb_sens" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="reg_wdi" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="rom_system_info" kind="avs_common_mm" version="1.0" enabled="1">
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ </module>
+ <module name="timer_0" kind="altera_avalon_timer" version="14.1" enabled="1">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="50000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ </module>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0188" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="cpu_0.debug_mem_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0180" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_remu.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00e0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_epcs.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0178" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_dpmm_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0170" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_ctrl.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0168" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="reg_mmdp_data.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0160" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0150" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0120" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0140" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.debug_mem_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="14.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="pio_debug_wave.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="pio_wdi.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="timer_0.clk" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="avs_eth_0.mm" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="pio_pps.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_wdi.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_remu.system" />
+ <connection kind="clock" version="14.1" start="clk_0.clk" end="reg_epcs.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_mmdp_data.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="clock"
+ version="14.1"
+ start="clk_0.clk"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="interrupt"
+ version="14.1"
+ start="cpu_0.irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="14.1"
+ start="cpu_0.irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="14.1" start="cpu_0.irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="timer_0.reset" />
+ <connection kind="reset" version="14.1" start="clk_0.clk_reset" end="cpu_0.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_mmdp_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="clk_0.clk_reset"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="cpu_0.reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_remu.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_epcs.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dpmm_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_data.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_dpmm_data.system_reset" />
+ <connection
+ kind="reset"
+ version="14.1"
+ start="cpu_0.debug_reset_request"
+ end="reg_mmdp_ctrl.system_reset" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
new file mode 100644
index 0000000000..730162e0df
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -0,0 +1,23 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+#source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_all_pins.tcl
+source $::env(RADIOHDL)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
new file mode 100644
index 0000000000..b8bfba4b2a
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -0,0 +1,275 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE unb2_board_lib.unb2_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE work.qsys_unb2_minimal_pkg.ALL;
+
+
+ENTITY mmm_unb2_minimal IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ pout_wdi : OUT STD_LOGIC;
+
+ -- Manual WDI override
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso;
+
+ -- system_info
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso;
+
+ -- eth1g
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso;
+ -- EPCS read
+ reg_dpmm_data_mosi : OUT t_mem_mosi;
+ reg_dpmm_data_miso : IN t_mem_miso;
+ reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
+ reg_dpmm_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS write
+ reg_mmdp_data_mosi : OUT t_mem_mosi;
+ reg_mmdp_data_miso : IN t_mem_miso;
+ reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
+ reg_mmdp_ctrl_miso : IN t_mem_miso;
+
+ -- EPCS status/control
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso;
+
+ -- Remote Update
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso
+ );
+END mmm_unb2_minimal;
+
+ARCHITECTURE str OF mmm_unb2_minimal IS
+
+ CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+
+ ----------------------------------------------------------------------------
+ -- mm_file component
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- QSYS for synthesis
+ ----------------------------------------------------------------------------
+ gen_qsys : IF g_sim = FALSE GENERATE
+ u_qsys : qsys_unb2_minimal
+ PORT MAP (
+
+ clk_clk => mm_clk,
+ reset_reset_n => mm_rst,
+
+ pio_debug_wave_external_connection_export => OPEN,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => OPEN,
+ avs_eth_0_clk_export => OPEN,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ pio_pps_reset_export => OPEN,
+ pio_pps_clk_export => OPEN,
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1),
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_address_export => reg_wdi_mosi.address(0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_remu_reset_export => OPEN,
+ reg_remu_clk_export => OPEN,
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_epcs_reset_export => OPEN,
+ reg_epcs_clk_export => OPEN,
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dpmm_ctrl_reset_export => OPEN,
+ reg_dpmm_ctrl_clk_export => OPEN,
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_mmdp_data_reset_export => OPEN,
+ reg_mmdp_data_clk_export => OPEN,
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dpmm_data_reset_export => OPEN,
+ reg_dpmm_data_clk_export => OPEN,
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_mmdp_ctrl_reset_export => OPEN,
+ reg_mmdp_ctrl_clk_export => OPEN,
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
new file mode 100644
index 0000000000..6bb3c81b00
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -0,0 +1,136 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE qsys_unb2_minimal_pkg IS
+
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+
+ COMPONENT qsys_unb2_minimal is
+ port (
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_debug_wave_external_connection_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic;--_vector(0 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic;--_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic;--_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic;--_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic;--_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic;--_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_reset_export : out std_logic -- export
+ );
+ END COMPONENT qsys_unb2_minimal;
+
+END qsys_unb2_minimal_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
new file mode 100644
index 0000000000..2745a6d31f
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -0,0 +1,307 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2_board_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+
+ENTITY unb2_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2_minimal";
+ g_design_note : STRING := "UNUSED";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+ );
+END unb2_minimal;
+
+
+ARCHITECTURE str OF unb2_minimal IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 1);
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb2_board_mm_clk_freq_50M,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => SENS_SC,
+ sens_sd => SENS_SD,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb2_minimal
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+ -----------------------------------------------------------------------------
+ -- Node function
+ -----------------------------------------------------------------------------
+ -- Insert node_[design_name] here
+
+END str;
+
diff --git a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
new file mode 100644
index 0000000000..350f67779e
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test.py
@@ -0,0 +1,355 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+"""Test case for unb1_minimal
+
+Usage:
+
+ --rep = number of intervals that diagnostics results are verified
+ --sim targets a running simulation.
+
+Description:
+ This test case tests:
+ - system info
+ - read sensors
+ - read ppsh
+ - write to wdi to force reload from bank 0
+ - flash access: write image to bank 1
+ - remote update: start image in bank 1
+
+"""
+
+###############################################################################
+# System imports
+import sys
+import signal
+import test_case
+import node_io
+import pi_system_info
+import pi_unb_sens
+import pi_ppsh
+import pi_wdi
+import pi_epcs
+import pi_remu
+import pi_eth
+import pi_debug_wave
+
+from tools import *
+from common import *
+from pi_common import *
+
+
+def test_info(tc,io,cmd):
+ tc.set_section_id('Read System Info - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ info = pi_system_info.PiSystemInfo(tc, io)
+ info.read_system_info()
+ tc.append_log(3, '')
+ info.read_use_phy()
+ tc.append_log(3, '')
+ design_name = info.read_design_name()
+ tc.append_log(1, '>>> design_name=%s' % design_name)
+ tc.append_log(3, '')
+ info.read_stamps()
+ tc.append_log(3, '')
+ info.read_design_note()
+
+ expected_design_name = tc.gpString
+ if expected_design_name != '':
+ tc.set_section_id('Verify System Info - ')
+ compared=True
+ for name in design_name:
+ if (name != expected_design_name):
+ tc.set_result('FAILED')
+ compared=False
+ tc.append_log(2, '>>> design_name mismatch!! (%s != %s)' % (name,expected_design_name))
+ tc.append_log(1, '>>> Verify design_name == %s: %s' % (expected_design_name,compared))
+
+
+
+def read_regmap(tc,io,cmd):
+ tc.set_section_id('Update REGMAP - ')
+ info = pi_system_info.PiSystemInfo(tc, io)
+ tc.append_log(1, '>>> reading REGMAPs')
+ info.make_register_info()
+ tc.append_log(1, '>>> reload NodeIO class')
+ return node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+
+
+def test_sensors(tc,io,cmd):
+ tc.set_section_id('Read sensors - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ sens = pi_unb_sens.PiUnbSens(tc, io)
+
+ sens.read_unb_sensors()
+ tc.append_log(3, '')
+ sens.read_fpga_temperature()
+ tc.append_log(3, '')
+ sens.read_eth_temperature()
+ tc.append_log(3, '')
+ sens.read_unb_current()
+ sens.read_unb_voltage()
+ sens.read_unb_power()
+
+
+
+def test_ppsh(tc,io,cmd):
+ tc.set_section_id('Read PPSH capture count - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Ppsh = pi_ppsh.PiPpsh(tc, io)
+ Ppsh.read_ppsh_capture_cnt()
+ tc.append_log(3, '')
+
+
+
+def test_wdi(tc,io,cmd):
+ tc.set_section_id('Reset to image in bank 0 using WDI - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Wdi = pi_wdi.PiWdi(tc, io)
+ Wdi.write_wdi_override()
+ tc.append_log(3, '')
+ tc.append_log(3, '>>> Booting...')
+ tc.sleep(5.0)
+
+
+
+def test_remu(tc,io,cmd):
+ tc.set_section_id('REMU start image in bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ dummy_tc = test_case.Testcase('Dummy TB - ', '',logfilename='REMU-log')
+ dummy_tc.set_result('PASSED')
+
+ Remu = pi_remu.PiRemu(dummy_tc, io)
+ try:
+ Remu.write_user_reconfigure()
+ except:
+ pass # ignoring FAILED
+
+ if dummy_tc.get_result() == 'FAILED':
+ tc.append_log(1, 'Result=%s but ignoring this' % dummy_tc.get_result())
+
+ tc.append_log(3, '>>> Booting...')
+ tc.sleep(5.0)
+ tc.append_log(3, '')
+
+
+
+def test_eth(tc,io,cmd):
+ tc.set_section_id('ETH status - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ eth = pi_eth.PiEth(tc, io)
+ hdr=eth.read_hdr(0)
+ eth.disassemble_hdr(hdr)
+ tc.append_log(3, '')
+
+
+
+def test_flash(tc,io,cmd):
+ tc.set_section_id('Flash write to bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+
+ Epcs = pi_epcs.PiEpcs(tc, io)
+ path_to_rbf = instanceName = tc.gpString
+ Epcs.write_raw_binary_file("user", path_to_rbf)
+ tc.append_log(3, '')
+
+ tc.set_section_id('Flash read/verify bank 1 - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> Read from flash (pi_epcs.py)')
+ tc.append_log(3, '>>>')
+
+ path_to_rbf = instanceName = tc.gpString
+ Epcs.read_and_verify_raw_binary_file("user", path_to_rbf)
+ tc.append_log(3, '')
+
+
+def set_led(tc,dw,led,text):
+ tc.append_log(3, text)
+ dw.set_led(led)
+ tc.sleep(1.0)
+
+def test_leds(tc,io,cmd):
+ tc.set_section_id('LED test - ')
+ tc.append_log(3, '>>>')
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ tc.append_log(3, '>>>')
+ dw = pi_debug_wave.PiDebugWave(tc, io)
+ set_led(tc,dw,'off', '')
+ set_led(tc,dw,'red', 'RED on')
+ set_led(tc,dw,'off', 'RED off')
+ set_led(tc,dw,'green','GREEN on')
+ set_led(tc,dw,'off', 'GREEN off')
+ set_led(tc,dw,'both', 'ORANGE (RED+GREEN) on')
+ set_led(tc,dw,'off', 'ORANGE (RED+GREEN) off')
+ tc.append_log(3, '')
+
+
+def sleep(tc,io,cmd):
+ tc.set_section_id('%s - ' % cmd)
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+ if cmd == 'sleep1':
+ tc.sleep(1.0)
+ elif cmd == 'sleep5':
+ tc.sleep(5.0)
+
+def show_help(tc,io,cmd):
+ tc.set_section_id('%s - ' % cmd)
+ tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
+
+
+# Avaliable commands
+Cmd = dict()
+Cmd['REGMAP'] = (read_regmap, 'using pi_system_info to read register info (access PIO_SYSTEM_INFO) and store REGMAPs','')
+Cmd['INFO'] = (test_info, 'using pi_system_info to read system info (access PIO_SYSTEM_INFO)','(-s for expected design_name)')
+Cmd['FLASH'] = (test_flash, 'using pi_epcs to program/verify flash','(-s for .rbf file)')
+Cmd['SENSORS'] = (test_sensors, 'using pi_unb_sens to readout sensors (access REG_UNB_SENS)','')
+Cmd['LED'] = (test_leds, 'using pi_debug_wave to set LEDs (access PIO_DEBUG_WAVE)','')
+Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (access PIO_PPS)','')
+Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','')
+Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','')
+Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
+Cmd['sleep1'] = (sleep, 'Sleep 1 second','')
+Cmd['sleep5'] = (sleep, 'Sleep 5 seconds','')
+Cmd['example'] = (show_help, 'show several example commands','')
+Cmd['help'] = (show_help, 'show help on commands','')
+
+
+def help_text(tc,io,cmd):
+ str=''
+ if cmd == 'help':
+ tc.append_log(0, '\n')
+ tc.append_log(0, '>>> Help:')
+ tc.append_log(0, 'Usage: %s <nodes> <command sequence> [-v..] [--rep ...]' % sys.argv[0])
+ tc.append_log(0, '')
+ tc.append_log(0, ' <nodes>: use: --unb N --fn N --bn N (N is a number or vector) or:')
+ tc.append_log(0, ' <nodes>: use: --gn N (N is a number or vector)')
+ tc.append_log(0, ' <command sequence>: use: --seq <command(s) separated by ",">:')
+ tc.append_log(0, '')
+ for cmd in sorted(Cmd):
+ tc.append_log(0, ' . %s\t%s %s' % (cmd,Cmd[cmd][1],Cmd[cmd][2]))
+ tc.append_log(0, '')
+ tc.append_log(0, ' [-vN]: verbose level N (default=5): %s' % tc.verbose_levels())
+ tc.append_log(0, ' [--rep N]: N=number of repeats, where -1 is forever, non-stop')
+ help_text(tc,io,'example')
+ elif cmd == 'example':
+ tc.append_log(0, '')
+ tc.append_log(0, '>>> Examples:')
+ tc.append_log(0, '')
+ tc.append_log(0, 'Getting INFO from all nodes on 1 Uniboard: %s --gn 0:7 --seq INFO' % sys.argv[0])
+ tc.append_log(0, '')
+ tc.append_log(0, '[reset, load user img] sequence: --seq REGMAP,WDI,REGMAP,REMU,REGMAP,INFO')
+ tc.append_log(0, '[flash+start user img] sequence: --seq FLASH,WDI,REGMAP,REMU,REGMAP,INFO -s file.rbf')
+ tc.append_log(0, '[re-read info,sensors] sequence: --seq INFO,PPSH,SENSORS --rep -1 -s expected_design_name')
+ tc.append_log(0, '[reset to factory] sequence: --seq WDI,REGMAP')
+ tc.append_log(0, '[program user image] sequence: --seq FLASH -s file.rbf')
+ tc.append_log(0, '[load user image] sequence: --seq REMU,REGMAP')
+ tc.append_log(0, '[modelsim BG-DB test] arguments: --unb 0 --fn 0 --seq BGDB --sim -r 0:2')
+ tc.append_log(0, '\n')
+ else:
+ str = Cmd[cmd][1]
+ return str
+
+
+def signal_handler(signal, frame):
+ print('You pressed Ctrl+C!')
+ tc.repeat=0
+
+
+##################################################################################################################
+# Main
+#
+# Create a test case object
+tc = test_case.Testcase('TB - ', '')
+tc.set_result('PASSED')
+dgnName = tc.gpString
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Title : Test bench (%s) on nodes %s, %s' % (sys.argv[0],tc.unb_nodes_string(''),dgnName))
+tc.append_log(0, '>>> Commandline : %s' % " ".join(sys.argv))
+tc.append_log(3, '>>>')
+
+
+# Create access object for nodes
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+signal.signal(signal.SIGINT, signal_handler)
+
+##################################################################################################################
+# Run tests
+while tc.repeat != 0: # -1 for non-stop
+ tc.repeat -= 1
+ tc.next_run()
+ tc.append_log(3, '')
+
+ try:
+ for cmd in tc.sequence:
+ tc.set_section_id('Next command: %s ' % cmd)
+ tc.append_log(1, '>>> Testrun %d (@%.02fs) - ' % (tc.get_nof_runs(),tc.get_run_time()))
+
+ if cmd == 'REGMAP': # reload node_io:
+ io = Cmd[cmd][0](tc,io,cmd)
+ else:
+ Cmd[cmd][0](tc,io,cmd)
+
+
+ except KeyError:
+ print 'Unknown command:',cmd
+ cmd='help'
+ Cmd[cmd][0](tc,io,cmd)
+# except:
+# print 'Catched error:',sys.exc_info()[0]
+
+
+
+##################################################################################################################
+# End
+tc.set_section_id('')
+tc.append_log(3, '')
+tc.append_log(3, '>>>')
+tc.append_log(0, '>>> Test bench result: %s' % tc.get_result())
+tc.append_log(0, '>>> Number of runs=%d' % tc.get_nof_runs())
+tc.append_log(0, '>>> Number of errors=%d' % tc.get_nof_errors())
+tc.append_log(0, '>>> Runtime=%f seconds (%f hours)' % (tc.get_run_time(),tc.get_run_time()/3600))
+tc.append_log(3, '>>>')
+
+sys.exit(tc.get_result())
+
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
new file mode 100644
index 0000000000..cf2e781b4c
--- /dev/null
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -0,0 +1,202 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for unb2_minimal.
+-- Description:
+-- The DUT can be targeted at unb 0, node 3 with the same Python scripts
+-- that are used on hardware.
+-- Usage:
+-- On command line do:
+-- > run_modelsim & (to start Modeslim)
+--
+-- In Modelsim do:
+-- > lp unb2_minimal
+-- > mk clean all (only first time to clean all libraries)
+-- > mk all (to compile all libraries that are needed for unb2_minimal)
+-- . load tb_unb1_minimal simulation by double clicking the tb_unb2_minimal icon
+-- > as 10 (to view signals in Wave Window)
+-- > run 100 us (or run -all)
+--
+-- On command line do:
+-- > python $UPE/peripherals/util_system_info.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE/peripherals/util_unb_sens.py --gn 3 -n 0 -v 5 --sim
+-- > python $UPE/peripherals/util_ppsh.py --gn 3 -n 1 -v 5 --sim
+--
+
+LIBRARY IEEE, common_lib, unb2_board_lib, i2c_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2_board_lib.unb2_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_unb2_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2_minimal";
+ g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
+ g_sim_node_nr : NATURAL := 3 -- Node 3
+ );
+END tb_unb2_minimal;
+
+ARCHITECTURE tb OF tb_unb2_minimal IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 3; -- Node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb2_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb2_board_nof_chip_w);
+
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2_board_fw_version := (1, 0);
+
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ -- DUT
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb2_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID : STD_LOGIC_VECTOR(c_unb2_board_aux.id_w-1 DOWNTO 0) := c_id;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb2_board_aux.testio_w-1 DOWNTO 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+
+ -- Model I2C sensor slaves as on the UniBoard
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01; -- = 10 mOhm on UniBoard
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_unb2_minimal : ENTITY work.unb2_minimal
+ GENERIC MAP (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_design_name => g_design_name
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp
+ );
+
+ ------------------------------------------------------------------------------
+ -- UniBoard sensors
+ ------------------------------------------------------------------------------
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA back node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+END tb;
--
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