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Commit 913beae8 authored by Eric Kooistra's avatar Eric Kooistra
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Made the script more generic by using command line arguments.

parent c2bc38d7
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...@@ -43,40 +43,55 @@ ...@@ -43,40 +43,55 @@
# 1) General tool and project settings # 1) General tool and project settings
# - use '. <script>.sh' to have the settings apply in this shell, otherwise they get lost when <script>.sh returns # - use '. <script>.sh' to have the settings apply in this shell, otherwise they get lost when <script>.sh returns
# Tool settings for selected target unb2 # Tool settings for selected target "", "unb1", or "unb2" (where "" defaults to target "unb1")
. ${RADIOHDL}/tools/quartus/set_quartus unb2 TARGET=${1:-}
. ${RADIOHDL}/tools/modelsim/set_modelsim unb2 if [ "${TARGET}" = "" ]; then
unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
fi
# Select output directory for the library compilation results # Select output directory for the library compilation results
OUTPUT_DIR=${1:-} OUTPUT_DIR=${2:-}
if [ "${OUTPUT_DIR}" = "" ]; then if [ "${OUTPUT_DIR}" = "" ]; then
unb_error $0 "Please specify an output directory" unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
fi
# Select FPGA device family for the library compilation
FAMILY=${3:-}
if [ "${FAMILY}" = "" ]; then
unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
fi fi
echo "Create Altera simulation libraries for Modelsim at output directory: ${OUTPUT_DIR}"
# Define the FPGA families echo ""
FAMILIES="arria10" echo "Create Altera libraries for simulation with the following settings:"
echo " - Tool target : ${TARGET}"
echo " - Output directory : ${OUTPUT_DIR}"
echo " - FPGA device family: ${FAMILY}"
echo ""
# Tool settings for selected target
. ${RADIOHDL}/tools/quartus/set_quartus ${TARGET}
. ${RADIOHDL}/tools/modelsim/set_modelsim ${TARGET}
# 2) Create Modelsim .do file for compiling the Altera simulation libraries # 2) Create Modelsim .do file for compiling the Altera simulation libraries
# . verilog # . verilog
quartus_sh --simlib_comp -family ${FAMILIES} \ quartus_sh --simlib_comp -family ${FAMILY} \
-tool modelsim \ -tool modelsim \
-tool_path $VSIM_DIR \ -tool_path $VSIM_DIR \
-language verilog \ -language verilog \
-directory ${OUTPUT_DIR} \ -directory ${OUTPUT_DIR} \
-log altera_simlibs_verilog.log \ -log ${FAMILY}_verilog.log \
-cmd_file altera_simlibs_verilog.do \ -cmd_file ${FAMILY}_verilog.do \
-gen_only \ -gen_only \
-suppress_messages -suppress_messages
# . vhdl # . vhdl
quartus_sh --simlib_comp -family ${FAMILIES} \ quartus_sh --simlib_comp -family ${FAMILY} \
-tool modelsim \ -tool modelsim \
-tool_path $VSIM_DIR \ -tool_path $VSIM_DIR \
-language vhdl \ -language vhdl \
-directory ${OUTPUT_DIR} \ -directory ${OUTPUT_DIR} \
-log altera_simlibs_vhdl.log \ -log ${FAMILY}_vhdl.log \
-cmd_file altera_simlibs_vhdl.do \ -cmd_file ${FAMILY}_vhdl.do \
-gen_only \ -gen_only \
-suppress_messages -suppress_messages
...@@ -84,8 +99,8 @@ quartus_sh --simlib_comp -family ${FAMILIES} \ ...@@ -84,8 +99,8 @@ quartus_sh --simlib_comp -family ${FAMILIES} \
cd ${OUTPUT_DIR} cd ${OUTPUT_DIR}
# Keep the log files # Keep the log files
mv ../altera_simlibs_verilog.log . mv ../${FAMILY}_verilog.log .
mv ../altera_simlibs_vhdl.log . mv ../${FAMILY}_vhdl.log .
# 3) Now use sed to replace 'vlib' by 'vlib -type directory' # 3) Now use sed to replace 'vlib' by 'vlib -type directory'
...@@ -103,9 +118,9 @@ mv ../altera_simlibs_vhdl.log . ...@@ -103,9 +118,9 @@ mv ../altera_simlibs_vhdl.log .
# #
# file.txt = the file name # file.txt = the file name
sed -i 's/vlib/vlib -type directory/g' altera_simlibs_verilog.do sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do
sed -i 's/vlib/vlib -type directory/g' altera_simlibs_vhdl.do sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do
# 4) Compile the Altera libraries with Modelsim # 4) Compile the Altera libraries with Modelsim
$VSIM_DIR/vsim -c -do altera_simlibs_verilog.do $VSIM_DIR/vsim -c -do ${FAMILY}_verilog.do
$VSIM_DIR/vsim -c -do altera_simlibs_vhdl.do $VSIM_DIR/vsim -c -do ${FAMILY}_vhdl.do
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