Made the script more generic by using command line arguments.

tools/quartus/run_altera_simlib_comp

@@ -43,40 +43,55 @@
 # 1) General tool and project settings
 # - use '. <script>.sh' to have the settings apply in this shell, otherwise they get lost when <script>.sh returns
 
-# Tool settings for selected target unb2
-. ${RADIOHDL}/tools/quartus/set_quartus unb2
-. ${RADIOHDL}/tools/modelsim/set_modelsim unb2
+# Tool settings for selected target "", "unb1", or "unb2" (where "" defaults to target "unb1")
+TARGET=${1:-}
+if [ "${TARGET}" = "" ]; then
+  unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
+fi
 
 # Select output directory for the library compilation results
-OUTPUT_DIR=${1:-}
+OUTPUT_DIR=${2:-}
 if [ "${OUTPUT_DIR}" = "" ]; then
-  unb_error $0 "Please specify an output directory"
+  unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
+fi
+
+# Select FPGA device family for the library compilation
+FAMILY=${3:-}
+if [ "${FAMILY}" = "" ]; then
+  unb_error $0 "Please specify all arguments\nUsage: $0 <tool target> <compilation output directory> <FPGA device family>"
 fi
-echo "Create Altera simulation libraries for Modelsim at output directory: ${OUTPUT_DIR}"
 
-# Define the FPGA families
-FAMILIES="arria10"
+echo ""
+echo "Create Altera libraries for simulation with the following settings:"
+echo "    - Tool target       : ${TARGET}"
+echo "    - Output directory  : ${OUTPUT_DIR}"
+echo "    - FPGA device family: ${FAMILY}"
+echo ""
+
+# Tool settings for selected target
+. ${RADIOHDL}/tools/quartus/set_quartus ${TARGET}
+. ${RADIOHDL}/tools/modelsim/set_modelsim ${TARGET}
 
 
 # 2) Create Modelsim .do file for compiling the Altera simulation libraries
 # . verilog
-quartus_sh --simlib_comp -family ${FAMILIES} \
+quartus_sh --simlib_comp -family ${FAMILY} \
                          -tool modelsim \
                          -tool_path $VSIM_DIR \
                          -language verilog \
                          -directory ${OUTPUT_DIR} \
-                         -log altera_simlibs_verilog.log \
-                         -cmd_file altera_simlibs_verilog.do \
+                         -log ${FAMILY}_verilog.log \
+                         -cmd_file ${FAMILY}_verilog.do \
                          -gen_only \
                          -suppress_messages
 # . vhdl
-quartus_sh --simlib_comp -family ${FAMILIES} \
+quartus_sh --simlib_comp -family ${FAMILY} \
                          -tool modelsim \
                          -tool_path $VSIM_DIR \
                          -language vhdl \
                          -directory ${OUTPUT_DIR} \
-                         -log altera_simlibs_vhdl.log \
-                         -cmd_file altera_simlibs_vhdl.do \
+                         -log ${FAMILY}_vhdl.log \
+                         -cmd_file ${FAMILY}_vhdl.do \
                          -gen_only \
                          -suppress_messages
                          
@@ -84,8 +99,8 @@ quartus_sh --simlib_comp -family ${FAMILIES} \
 cd ${OUTPUT_DIR}
 
 # Keep the log files
-mv ../altera_simlibs_verilog.log .
-mv ../altera_simlibs_vhdl.log .
+mv ../${FAMILY}_verilog.log .
+mv ../${FAMILY}_vhdl.log .
 
 
 # 3) Now use sed to replace 'vlib' by 'vlib -type directory'
@@ -103,9 +118,9 @@ mv ../altera_simlibs_vhdl.log .
 #
 #    file.txt = the file name 
 
-sed -i 's/vlib/vlib -type directory/g' altera_simlibs_verilog.do
-sed -i 's/vlib/vlib -type directory/g' altera_simlibs_vhdl.do
+sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do
+sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do
 
 # 4) Compile the Altera libraries with Modelsim
-$VSIM_DIR/vsim -c -do altera_simlibs_verilog.do
-$VSIM_DIR/vsim -c -do altera_simlibs_vhdl.do
+$VSIM_DIR/vsim -c -do ${FAMILY}_verilog.do
+$VSIM_DIR/vsim -c -do ${FAMILY}_vhdl.do