clk200 pll should be a fpll for ddr4

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -346,6 +346,7 @@ BEGIN
       u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
       GENERIC MAP (
         g_technology          => g_technology,
+        g_use_fpll            => TRUE,
         g_clk200_phase_shift  => g_dp_clk_phase
       )
       PORT MAP (