From 8fec003692f09456f0566e50cc77aca0c217091c Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Mon, 15 Jun 2015 10:00:45 +0000
Subject: [PATCH] clk200 pll should be a fpll for ddr4
---
.../uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd | 1 +
1 file changed, 1 insertion(+)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 086ec77851..a26f214f13 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -346,6 +346,7 @@ BEGIN
u_unb2_board_clk200_pll : ENTITY work.unb2_board_clk200_pll
GENERIC MAP (
g_technology => g_technology,
+ g_use_fpll => TRUE,
g_clk200_phase_shift => g_dp_clk_phase
)
PORT MAP (
--
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