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Commit 8f0857e1 authored by Pepping's avatar Pepping
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-Update the library section 

- Added tech generics
- Removed old ddr3 generics
- Updated porttypes
- replaced ddr3 by io_ddr
parent 2c1a6f94
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libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+ 106
− 100
View file @ 8f0857e1
......@@ -20,17 +20,21 @@
--
--------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, ss_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
LIBRARY IEEE, technology_lib, common_lib, dp_lib, io_ddr_lib, tech_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.ddr3_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.reorder_pkg.ALL;
ENTITY ddr3_transpose IS
ENTITY reorder_transpose IS
GENERIC(
g_sim : BOOLEAN := FALSE;
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_nof_streams : NATURAL := 4;
g_in_dat_w : NATURAL := 8;
g_frame_size_in : NATURAL := 256;
......@@ -38,9 +42,7 @@ ENTITY ddr3_transpose IS
g_nof_blk_per_sync : NATURAL := 16;
g_use_complex : BOOLEAN := TRUE;
g_ena_pre_transp : BOOLEAN := TRUE;
g_phy : NATURAL := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
g_mts : NATURAL := 800; -- Megatransfers per second
g_ddr3_seq : t_ddr3_seq := c_ddr3_seq;
g_reorder_seq : t_reorder_seq := c_reorder_seq;
g_select_file : STRING := "UNUSED"
);
PORT (
......@@ -66,47 +68,47 @@ ENTITY ddr3_transpose IS
ser_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
par_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
phy_in : IN t_ddr3_phy_in;
phy_io : INOUT t_ddr3_phy_io;
phy_ou : OUT t_ddr3_phy_ou
); https://kickass.so/the-tracker-2002-x264-aac-t5162938.html
END ddr3_transpose;
phy_in : IN t_tech_ddr_phy_in := c_tech_ddr_phy_in_x;
phy_io : INOUT t_tech_ddr_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou
);
END reorder_transpose;
ARCHITECTURE str OF ddr3_transpose IS
ARCHITECTURE str OF reorder_transpose IS
CONSTANT c_min_fifo_size : POSITIVE := 256;
CONSTANT c_blocksize : POSITIVE := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;
CONSTANT c_blocksize : POSITIVE := g_reorder_seq.wr_nof_chunks * (g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize);
CONSTANT c_pagesize : POSITIVE := g_reorder_seq.nof_blocks * c_blocksize;
CONSTANT c_mem_size : POSITIVE := 2*c_pagesize;
CONSTANT c_mem_size_w : POSITIVE := ceil_log2(c_mem_size);
CONSTANT c_wr_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_rd_fifo_depth : NATURAL := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size);--c_blocksize * 2;
CONSTANT c_total_data_w : NATURAL := g_nof_streams*g_in_dat_w;
CONSTANT c_complex_data_w : NATURAL := c_total_data_w*c_nof_complex;
CONSTANT c_data_w : NATURAL := sel_a_b(g_use_complex, c_complex_data_w, c_total_data_w);
CONSTANT c_nof_ch_in : NATURAL := g_frame_size_in*g_ddr3_seq.rd_chunksize;
CONSTANT c_nof_ch_sel : NATURAL := c_nof_ch_in;
CONSTANT c_cnt_sop_w : NATURAL := ceil_log2(g_nof_blk_per_sync)+1;
CONSTANT c_total_data_w : NATURAL := g_nof_streams*g_in_dat_w;
CONSTANT c_complex_data_w : NATURAL := c_total_data_w*c_nof_complex;
CONSTANT c_data_w : NATURAL := sel_a_b(g_use_complex, c_complex_data_w, c_total_data_w);
CONSTANT c_nof_ch_in : NATURAL := g_frame_size_in*g_reorder_seq.rd_chunksize;
CONSTANT c_nof_ch_sel : NATURAL := c_nof_ch_in;
CONSTANT c_cnt_sop_w : NATURAL := ceil_log2(g_nof_blk_per_sync)+1;
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
CONSTANT c_data_w_ratio : POSITIVE := c_ctlr_data_w/c_data_w;
SIGNAL ss_in_sosi : t_dp_sosi;
SIGNAL ss_in_siso : t_dp_siso;
-- ctrl & status DDR3 driver
SIGNAL dvr_start_addr : t_ddr3_addr;
SIGNAL dvr_end_addr : t_ddr3_addr;
SIGNAL dvr_done : STD_LOGIC;
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
SIGNAL dvr_start_address : STD_LOGIC_VECTOR(c_mem_size_w-1 DOWNTO 0);
SIGNAL dvr_nof_data : STD_LOGIC_VECTOR(c_mem_size_w-1 DOWNTO 0);
SIGNAL dvr_wr_flush_en : STD_LOGIC;
SIGNAL flush_ena : STD_LOGIC;
-- DDR3 controller status
SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL init_done_data_start : STD_LOGIC;
SIGNAL transpose_in_sosi : t_dp_sosi;
SIGNAL transpose_in_siso : t_dp_siso;
......@@ -115,6 +117,9 @@ ARCHITECTURE str OF ddr3_transpose IS
SIGNAL block_gen_out_sosi : t_dp_sosi;
SIGNAL pipeline_out_sosi : t_dp_sosi;
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL sync_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL wr_req : STD_LOGIC;
SIGNAL rd_req_i : STD_LOGIC;
......@@ -127,6 +132,9 @@ ARCHITECTURE str OF ddr3_transpose IS
SIGNAL nxt_mon_nof_sop : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
SIGNAL sync_ok_in : STD_LOGIC;
SIGNAL sync_ok_out : STD_LOGIC;
SIGNAL ctlr_clk : STD_LOGIC;
SIGNAL ctlr_rst : STD_LOGIC;
BEGIN
......@@ -152,7 +160,7 @@ BEGIN
-- END GENERATE;
gen_pre_transpose : IF g_ena_pre_transp = TRUE GENERATE
u_single_ss : ENTITY ss_lib.ss
u_single_ss : ENTITY work.ss
GENERIC MAP (
g_dsp_data_w => c_total_data_w,
g_nof_ch_in => c_nof_ch_in,
......@@ -188,75 +196,75 @@ BEGIN
snk_out_arr(J) <= ss_in_siso;
END GENERATE;
u_ddr3: ENTITY work.ddr3
GENERIC MAP(
g_ddr => c_ddr3_phy_4g,
g_phy => g_phy,
g_mts => g_mts,
g_wr_data_w => c_data_w,
g_wr_use_ctrl => TRUE,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_data_w,
g_flush_wr_fifo => TRUE,
g_flush_ext_ena => TRUE,
g_flush_sop => TRUE,
g_flush_sop_sync => TRUE,
g_flush_sop_channel => FALSE,
g_flush_sop_start_channel => 0,
g_flush_nof_channels => 0
u_ddr3: ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_sim => g_sim,
g_technology => g_technology, -- : NATURAL := c_tech_select_default;
g_tech_ddr => g_tech_ddr, -- : t_c_tech_ddr;
g_cross_domain_dvr_ctlr => FALSE, --TRUE, -- : BOOLEAN := TRUE;
g_wr_data_w => c_data_w, -- : NATURAL := 32;
g_wr_fifo_depth => c_wr_fifo_depth, -- : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
g_rd_fifo_depth => c_rd_fifo_depth, -- : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
g_rd_data_w => c_data_w, -- : NATURAL := 32;
g_wr_flush_mode => "SYN", -- : STRING := "VAL"; -- "VAL", "SOP", "SYN"
g_wr_flush_use_channel => FALSE, -- : BOOLEAN := FALSE;
g_wr_flush_start_channel => 0, -- : NATURAL := 0;
g_wr_flush_nof_channels => 1 -- : POSITIVE := 1
)
PORT MAP (
ctlr_ref_clk => dp_clk,
ctlr_rst => dp_rst,
PORT MAP (
-- DDR reference clock
ctlr_ref_clk => dp_clk,
ctlr_ref_rst => dp_rst,
phy_in => phy_in,
phy_io => phy_io,
phy_ou => phy_ou,
ctlr_gen_clk => OPEN,
ctlr_gen_rst => OPEN,
ctlr_init_done => ctlr_init_done,
ctlr_rdy => ctlr_rdy,
dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr,
dvr_done => dvr_done,
dvr_wr_not_rd => dvr_wr_not_rd,
dvr_en => dvr_en,
-- DDR controller clock domain
ctlr_clk_out => ctlr_clk,
ctlr_rst_out => ctlr_rst,
wr_clk => dp_clk,
wr_rst => dp_rst,
ctlr_clk_in => ctlr_clk, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
ctlr_rst_in => ctlr_rst, -- connect ctlr_rst_out to ctlr_rst_in at top level
wr_sosi => transpose_in_sosi,
wr_siso => transpose_in_siso,
-- Driver clock domain
dvr_clk => dp_clk,
dvr_rst => dp_rst,
flush_ena => flush_ena,
rd_sosi => transpose_out_sosi,
rd_siso => src_in_arr(0),
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
rd_clk => dp_clk,
rd_rst => dp_rst,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
ser_term_ctrl_out => ser_term_ctrl_out,
par_term_ctrl_out => par_term_ctrl_out,
ser_term_ctrl_in => ser_term_ctrl_in,
par_term_ctrl_in => par_term_ctrl_in,
wr_fifo_usedw => OPEN,
wr_sosi => transpose_in_sosi,
wr_siso => transpose_in_siso,
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => OPEN,
rd_sosi => transpose_out_sosi,
rd_siso => src_in_arr(0),
rd_fifo_usedw => OPEN
phy_in => phy_in,
phy_io => phy_io,
phy_ou => phy_ou
);
flush_ena <= NOT(ctlr_init_done) OR NOT(sync_ok_out);
init_done_data_start <= ctlr_init_done AND transpose_in_sosi.sync;
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
dvr_done <= ctlr_dvr_miso.done; -- Requested wr or rd sequence is done
ctlr_dvr_mosi.burstbegin <= dvr_en;
ctlr_dvr_mosi.wr <= dvr_wr_not_rd; -- No need to use dvr_mosi.rd
ctlr_dvr_mosi.address <= RESIZE_MEM_CTLR_ADDRESS(dvr_start_address);
ctlr_dvr_mosi.burstsize <= RESIZE_MEM_CTLR_BURSTSIZE(dvr_nof_data);
ctlr_dvr_mosi.flush <= dvr_wr_flush_en;
dvr_wr_flush_en <= NOT(sync_ok_out);
u_ddr3_sequencer: ENTITY work.ddr3_seq
u_ddr_sequencer: ENTITY work.reorder_sequencer
GENERIC MAP(
g_ddr => c_ddr3_phy_4g,
g_ddr3_seq => g_ddr3_seq
g_reorder_seq => g_reorder_seq,
g_data_w_ratio => c_data_w_ratio
)
PORT MAP (
dp_rst => dp_rst,
......@@ -265,12 +273,10 @@ BEGIN
en_evt => dvr_en,
wr_not_rd => dvr_wr_not_rd,
start_addr => dvr_start_addr,
end_addr => dvr_end_addr,
address => dvr_start_address,
burstsize => dvr_nof_data,
done => dvr_done,
init_done => init_done_data_start,
ctlr_rdy => ctlr_rdy,
done => dvr_done,
sync_ok_in => sync_ok_in,
sync_ok_out => sync_ok_out
......@@ -304,7 +310,7 @@ BEGIN
---------------------------------------------------------------
-- FIFO FOR SYNC-BSN
---------------------------------------------------------------
wr_req <= snk_in_arr(0).sync AND ctlr_init_done;
wr_req <= snk_in_arr(0).sync;
u_sync_bsn_fifo : ENTITY common_lib.common_fifo_sc
GENERIC MAP (
......
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