Default sens_sc/sd = 'H'. Create ref_rst for MB ref_clk.

boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd

@@ -117,21 +117,24 @@ ENTITY ctrl_unb2_board IS
     cs_sim                 : OUT STD_LOGIC;
     
     xo_ethclk              : OUT STD_LOGIC;   -- 125 MHz ETH_CLK
-    xo_rst                 : OUT STD_LOGIC;
+    xo_rst                 : OUT STD_LOGIC;   -- reset in ETH_CLK domain released after few cycles
     xo_rst_n               : OUT STD_LOGIC; 
    
     ext_clk200             : OUT STD_LOGIC;   -- 200 MHz CLK
-    ext_rst200             : OUT STD_LOGIC;
+    ext_rst200             : OUT STD_LOGIC;   -- reset in CLK clock domain released after mm_rst
     
     mm_clk                 : OUT STD_LOGIC;   -- MM clock from xo_ethclk PLL
-    mm_rst                 : OUT STD_LOGIC;
+    mm_rst                 : OUT STD_LOGIC;   -- reset in MM clock domain released after xo_ethclk PLL locked
     
-    dp_rst                 : OUT STD_LOGIC;
-    dp_clk                 : OUT STD_LOGIC;   -- 200 MHz from CLK system clock direct or via PLL dependent on g_dp_clk_use_pll
+    dp_rst                 : OUT STD_LOGIC;   -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+    dp_clk                 : OUT STD_LOGIC;   -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
     dp_pps                 : OUT STD_LOGIC;   -- PPS in dp_clk domain
     dp_rst_in              : IN  STD_LOGIC;   -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
     dp_clk_in              : IN  STD_LOGIC;   -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
 
+    mb_I_ref_rst           : OUT STD_LOGIC;   -- reset in MB_I_REF_CLK domain released after mm_rst
+    mb_II_ref_rst          : OUT STD_LOGIC;   -- reset in MB_II_REF_CLK domain released after mm_rst
+    
     this_chip_id           : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_chip_w-1 DOWNTO 0);      -- [1:0], so range 0-3 for PN
     this_bck_id            : OUT STD_LOGIC_VECTOR(c_unb2_board_nof_uniboard_w-1 DOWNTO 0);  -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
     
@@ -212,13 +215,17 @@ ENTITY ctrl_unb2_board IS
     TESTIO                 : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
     
     -- I2C Interface to Sensors
-    SENS_SC                : INOUT STD_LOGIC := '1';
-    SENS_SD                : INOUT STD_LOGIC := '1';
+    SENS_SC                : INOUT STD_LOGIC := 'H';
+    SENS_SD                : INOUT STD_LOGIC := 'H';
+    
+    -- DDR reference clock domains reset creation
+    MB_I_REF_CLK           : IN    STD_LOGIC := '0';  -- 25 MHz
+    MB_II_REF_CLK          : IN    STD_LOGIC := '0';  -- 25 MHz
     
     -- 1GbE Control Interface
     ETH_CLK                : IN    STD_LOGIC;  -- 125 MHz
     ETH_SGIN               : IN    STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0) := (OTHERS=>'0');
-    ETH_SGOUT              : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)
+    ETH_SGOUT              : OUT   STD_LOGIC_VECTOR(c_unb2_board_nof_eth-1 DOWNTO 0)    
   );
 END ctrl_unb2_board;
 
@@ -321,6 +328,33 @@ BEGIN
   );
 
 
+  -----------------------------------------------------------------------------
+  -- MB_I_REF_CLK  --> mb_I_ref_rst
+  -- MB_II_REF_CLK --> mb_II_ref_rst
+  -----------------------------------------------------------------------------
+  
+  u_common_areset_mb_I : ENTITY common_lib.common_areset
+  GENERIC MAP (
+    g_rst_level => '1',       -- power up default will be inferred in FPGA
+    g_delay_len => c_reset_len
+  )
+  PORT MAP (
+    in_rst    => i_mm_rst,   -- release reset some clock cycles after i_mm_rst went low
+    clk       => MB_I_REF_CLK,
+    out_rst   => mb_I_ref_rst
+  );
+  
+  u_common_areset_mb_II : ENTITY common_lib.common_areset
+  GENERIC MAP (
+    g_rst_level => '1',       -- power up default will be inferred in FPGA
+    g_delay_len => c_reset_len
+  )
+  PORT MAP (
+    in_rst    => i_mm_rst,   -- release reset some clock cycles after i_mm_rst went low
+    clk       => MB_II_REF_CLK,
+    out_rst   => mb_II_ref_rst
+  );
+  
   -----------------------------------------------------------------------------
   -- dp_clk
   -- . release dp_rst some clock cycles after mm_rst went low