Merge branch 'master' into RTSD-265

applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl

@@ -58,6 +58,34 @@ set_location_assignment PIN_BB5 -to BCK_RX[2]
 set_location_assignment PIN_AY9 -to BCK_RX[1]
 set_location_assignment PIN_BB9 -to BCK_RX[0]
 
+# Set link type to Long Reach (LR) for Backplane communication.
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[0]
+
+# Set Equalizer to high gain mode.
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[11]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[10]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[9]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[8]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[7]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[6]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[5]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[4]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[0]
+
 set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   BCK_TX[0]
 set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  BCK_TX[0]
 set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           BCK_TX[0]

applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys

@@ -33260,7 +33260,7 @@
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip</parameter>
+  <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>

applications/lofar2/images/images.txt

@@ -50,6 +50,7 @@ lofar2_unb2c_sdp_station_full-dbc6375ef         | 2024-02-22 | EK   | See [1]. O
 
 lofar2_unb2c_sdp_station_full-d601da896         | 2024-03-02 | EK   | With 1024 size input buffer
 lofar2_unb2b_sdp_station_full_wg-d601da896      | 2024-03-02 | EK   | With 1024 size input buffer
+lofar2_unb2c_sdp_station_full-3b0adbdd1         | 2024-07-31 | RW   | Added JESD RX assignments LR + non_s1_mode
 
 References:
 [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+SDP+FW+general

libraries/base/common/src/vhdl/common_areset.vhd

@@ -22,15 +22,30 @@
 -- Author: E. Kooistra
 -- Purpose: Immediately apply reset and synchronously release it at rising clk
 -- Description:
---   When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply).
---   When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous
---   reset release) + g_tree_len cycles (synchronous reset tree).
+--   When in_rst gets asserted, then the out_rst gets asserted immediately (=
+--   asynchronous reset apply).
+--   When in_rst gets de-assered, then out_rst gets de-asserted after
+--   g_delay_len cycles (= synchronous reset release) + g_tree_len cycles
+--   (synchronous reset tree).
 --
 --   The in_rst assert level is set by g_in_rst_level.
 --   The out_rst assert level is set by c_out_rst_level = g_rst_level.
 --
+-- * g_delay_len: Long enough to ensure that the o_rst output of u_async has
+--   recovered from meta-stability that can occur when a flipflop (FF) clocks
+--   in the asynchrounous in_rst while it changes level.
+-- * g_tree_len:
+--   . Use g_tree_len = 0 to only have u_async, so with asynchrounous path from
+--     in_rst to out_rst.
+--   . Use g_tree_len = 1 to only have u_pipe of one flipflop (FF) to break the
+--     asynchronous path, but with only one clk cycle extra latency.
+--   . Use g_tree_len = c_tree_delay_len >> 1 to have a multi stage FF delay
+--     line that can be expanded into a synchronous reset tree by means of FF
+--     register duplication by the synthesis tool. The multi stage register
+--     duplication eases timing closure in case of large fanout for out_rst.
 -- Remarks:
--- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
+-- . The in_rst can also synchronise other signals than a reset, e.g. a locked
+--   signal from a PLL.
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -42,7 +57,7 @@ entity common_areset is
     g_rst_level    : std_logic := '1';  -- = out_rst level (keep original generic
                                         --   name for backward compatibility)
     g_delay_len    : natural := c_meta_delay_len;
-    g_tree_len     : natural := c_tree_delay_len
+    g_tree_len     : natural := 1
   );
   port (
     in_rst    : in  std_logic;
@@ -64,6 +79,7 @@ begin
   -- 2009
   -- Capture asynchronous reset assertion, to also support i_rst when there is
   -- no clk.
+  without_pipe : if g_tree_len = 0 generate
     u_async : entity work.common_async
     generic map (
       g_rst_level => c_out_rst_level,
@@ -73,24 +89,41 @@ begin
       rst  => i_rst,
       clk  => clk,
       din  => c_out_rst_level_n,
-    dout => o_rst
+      dout => out_rst
     );
+  end generate;
 
   -- 2024
   -- Pass on synchronized reset with sufficient g_tree_len to ease timing
   -- closure by FF duplication in out_rst tree. Keep rst = '0' to break
   -- combinatorial path with in_rst to ease timing closure in the reset tree
-  -- network. Use g_tree_len = 0 for wire out_rst <= o_rst, so no reset tree
-  -- as in 2009.
-  u_pipe : entity work.common_pipeline_sl
+  -- network. Use g_tree_len = 0 for no clocked reset tree as in 2009.
+  -- Instantiate u_async again to keep 2009 and 2024 completely independent.
+  -- To avoid delta-cycle differences due to e.g. out_rst <= o_rst when
+  -- g_tree_len = 0, that could lead to different results in a simulation tb.
+  with_pipe : if g_tree_len > 0 generate
+    u_async : entity work.common_async
+    generic map (
+      g_rst_level => c_out_rst_level,
+      g_delay_len => g_delay_len
+    )
+    port map (
+      rst  => i_rst,
+      clk  => clk,
+      din  => c_out_rst_level_n,
+      dout => o_rst
+    );
+
+    u_pipe : entity work.common_async
     generic map (
-    g_pipeline    => g_tree_len,
-    g_reset_value => c_out_rst_value
+      g_rst_level => c_out_rst_level,
+      g_delay_len => g_tree_len  -- must be positive in common_async
     )
     port map (
       rst  => '0',
       clk  => clk,
-    in_dat  => o_rst,
-    out_dat => out_rst
+      din  => o_rst,
+      dout => out_rst
     );
+  end generate;
 end str;

libraries/base/common/src/vhdl/common_fifo_dc.vhd

@@ -75,7 +75,8 @@ begin
   u_wr_rst : entity work.common_areset
   generic map (
     g_rst_level => '1',
-    g_delay_len => 3
+    g_delay_len => 3,
+    g_tree_len  => 0  -- assume if necessary g_tree_len > 0 is covered via input rst
   )
   port map (
     in_rst    => rst,
@@ -87,7 +88,8 @@ begin
   u_wr_init : entity work.common_areset
   generic map (
     g_rst_level => '1',
-    g_delay_len => 4
+    g_delay_len => 4,
+    g_tree_len  => 0
   )
   port map (
     in_rst  => wr_rst,

libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd

@@ -94,7 +94,8 @@ begin
   u_wr_rst : entity work.common_areset
   generic map (
     g_rst_level => '1',
-    g_delay_len => 3
+    g_delay_len => 3,
+    g_tree_len  => 0  -- assume if necessary g_tree_len > 0 is covered via input rst
   )
   port map (
     in_rst    => rst,
@@ -106,7 +107,8 @@ begin
   u_wr_init : entity work.common_areset
   generic map (
     g_rst_level => '1',
-    g_delay_len => 4
+    g_delay_len => 4,
+    g_tree_len  => 0
   )
   port map (
     in_rst  => wr_rst,

libraries/base/common/src/vhdl/common_fifo_sc.vhd

@@ -83,7 +83,8 @@ begin
     u_fifo_rst : entity work.common_areset
     generic map (
       g_rst_level => '1',
-      g_delay_len => 4
+      g_delay_len => 4,
+      g_tree_len  => 0  -- assume if necessary g_tree_len > 0 is covered via input rst
     )
     port map (
       in_rst    => rst,
@@ -101,7 +102,8 @@ begin
     u_fifo_init : entity work.common_areset
     generic map (
       g_rst_level => '1',
-      g_delay_len => 4
+      g_delay_len => 4,
+      g_tree_len  => 0
     )
     port map (
       in_rst    => fifo_rst,

libraries/base/reorder/src/vhdl/reorder_transpose.vhd

@@ -368,8 +368,6 @@ begin
   u_sync_bsn_fifo : entity common_lib.common_fifo_sc
   generic map (
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 2 words deep.
-    g_reset     => false,
-    g_init      => false,
     g_dat_w     => c_dp_stream_bsn_w,
     g_nof_words => 4  -- 2 sync intervals should be sufficient, choose 4 to be safe (erko)
   )

libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd

@@ -96,8 +96,6 @@ begin
   u_bsn_fifo : entity common_lib.common_fifo_sc
   generic map (
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 4 words deep.
-    g_reset     => false,
-    g_init      => false,
     g_dat_w     => c_dp_stream_bsn_w,
     g_nof_words => c_ctrl_fifo_depth
   )
@@ -120,8 +118,6 @@ begin
   u_error_fifo : entity common_lib.common_fifo_sc
   generic map (
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 4 words deep.
-    g_reset     => false,
-    g_init      => false,
     g_dat_w     => c_dp_stream_error_w,
     g_nof_words => c_ctrl_fifo_depth
   )
@@ -144,8 +140,6 @@ begin
   u_sync_bsn_fifo : entity common_lib.common_fifo_sc
   generic map (
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 4 words deep.
-    g_reset     => false,
-    g_init      => false,
     g_dat_w     => c_dp_stream_bsn_w,
     g_nof_words => 2
   )

libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd

@@ -158,7 +158,7 @@ begin
   proc_common_gen_data(c_rl, c_init, rst, s_clk, cnt_en, ready, in_dat, in_val);
 
   -- Verify data
-  verify_data_en  <= verify_en or dp_locked;
+  verify_data_en  <= verify_en and dp_locked;
   verify_phase_en <= verify_en;
 
   proc_common_verify_data(c_rl, dp_sclk, verify_data_en, ready, dp_val, dp_sample_dat, prev_dp_sample_dat);

libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd

@@ -324,8 +324,6 @@ begin
   u_sync_bsn_fifo : entity common_lib.common_fifo_sc
   generic map (
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 2 words deep.
-    g_reset     => false,
-    g_init      => false,
     g_dat_w     => c_dp_stream_bsn_w,
     g_nof_words => 16
   )