diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl index 4c1458f377e0f097733b6f7c81d1fac5c730a511..68493f020ab05975213c3816ebd9d059da72bc22 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl @@ -58,6 +58,34 @@ set_location_assignment PIN_BB5 -to BCK_RX[2] set_location_assignment PIN_AY9 -to BCK_RX[1] set_location_assignment PIN_BB9 -to BCK_RX[0] +# Set link type to Long Reach (LR) for Backplane communication. +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[11] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[10] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[9] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[8] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[7] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[6] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[5] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[4] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[3] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[2] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[1] +set_instance_assignment -name XCVR_A10_RX_LINK LR -to BCK_RX[0] + +# Set Equalizer to high gain mode. +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[11] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[10] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[9] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[8] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[7] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[6] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[5] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[4] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[3] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[2] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[1] +set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[0] + set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0] set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0] set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0] diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys index 1e2eb5123971ca96dc706fc9664afb6afaa54ed1..0d55fa4b896fc27be44f91a74f70ee76c2e5b36f 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys @@ -33260,7 +33260,7 @@ </fileSets> </generationInfoDefinition>]]></parameter> <parameter name="hlsFile" value="" /> - <parameter name="logicalView">ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip</parameter> + <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bdo_destinations.ip</parameter> <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition> <assignmentValueMap/> </assignmentDefinition>]]></parameter> diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt index 8b2961a16b1d75adb95dbead3dbe7703ecd7f4c0..4b08358b00403aa6a838af225d6fd0f5d0b38e73 100644 --- a/applications/lofar2/images/images.txt +++ b/applications/lofar2/images/images.txt @@ -50,6 +50,7 @@ lofar2_unb2c_sdp_station_full-dbc6375ef | 2024-02-22 | EK | See [1]. O lofar2_unb2c_sdp_station_full-d601da896 | 2024-03-02 | EK | With 1024 size input buffer lofar2_unb2b_sdp_station_full_wg-d601da896 | 2024-03-02 | EK | With 1024 size input buffer +lofar2_unb2c_sdp_station_full-3b0adbdd1 | 2024-07-31 | RW | Added JESD RX assignments LR + non_s1_mode References: [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+SDP+FW+general diff --git a/applications/lofar2/images/lofar2_unb2c_sdp_station_full-3b0adbdd1.tar.gz b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-3b0adbdd1.tar.gz new file mode 100644 index 0000000000000000000000000000000000000000..a050afef6adc02c34db3818cb9d9ed592c9c3559 Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-3b0adbdd1.tar.gz differ diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt index 07fe7059f695ca790b2fcf570be16c9c4f5782b4..a810dee399b16b315e7995c5d4fa0816463bb5aa 100755 --- a/doc/erko_howto_tools.txt +++ b/doc/erko_howto_tools.txt @@ -1637,7 +1637,7 @@ Fetched 185 kB in 1s (191 kB/s) Reading package lists... Done > sudo apt-get install openscad -Gelukt ! +Gelukt! ******************************************************************************* diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd index 57cc27cb308c6a760b2a8dde1b7d37d4f908d468..a1ee86812bf3c6d3d2d53233be9f5f3043b9b7bf 100644 --- a/libraries/base/common/src/vhdl/common_areset.vhd +++ b/libraries/base/common/src/vhdl/common_areset.vhd @@ -22,15 +22,30 @@ -- Author: E. Kooistra -- Purpose: Immediately apply reset and synchronously release it at rising clk -- Description: --- When in_rst gets asserted, then the out_rst gets asserted immediately (= asynchronous reset apply). --- When in_rst gets de-assered, then out_rst gets de-asserted after g_delay_len cycles (= synchronous --- reset release) + g_tree_len cycles (synchronous reset tree). +-- When in_rst gets asserted, then the out_rst gets asserted immediately (= +-- asynchronous reset apply). +-- When in_rst gets de-assered, then out_rst gets de-asserted after +-- g_delay_len cycles (= synchronous reset release) + g_tree_len cycles +-- (synchronous reset tree). -- -- The in_rst assert level is set by g_in_rst_level. -- The out_rst assert level is set by c_out_rst_level = g_rst_level. -- +-- * g_delay_len: Long enough to ensure that the o_rst output of u_async has +-- recovered from meta-stability that can occur when a flipflop (FF) clocks +-- in the asynchrounous in_rst while it changes level. +-- * g_tree_len: +-- . Use g_tree_len = 0 to only have u_async, so with asynchrounous path from +-- in_rst to out_rst. +-- . Use g_tree_len = 1 to only have u_pipe of one flipflop (FF) to break the +-- asynchronous path, but with only one clk cycle extra latency. +-- . Use g_tree_len = c_tree_delay_len >> 1 to have a multi stage FF delay +-- line that can be expanded into a synchronous reset tree by means of FF +-- register duplication by the synthesis tool. The multi stage register +-- duplication eases timing closure in case of large fanout for out_rst. -- Remarks: --- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL. +-- . The in_rst can also synchronise other signals than a reset, e.g. a locked +-- signal from a PLL. library IEEE; use IEEE.std_logic_1164.all; @@ -42,7 +57,7 @@ entity common_areset is g_rst_level : std_logic := '1'; -- = out_rst level (keep original generic -- name for backward compatibility) g_delay_len : natural := c_meta_delay_len; - g_tree_len : natural := c_tree_delay_len + g_tree_len : natural := 1 ); port ( in_rst : in std_logic; @@ -64,33 +79,51 @@ begin -- 2009 -- Capture asynchronous reset assertion, to also support i_rst when there is -- no clk. - u_async : entity work.common_async - generic map ( - g_rst_level => c_out_rst_level, - g_delay_len => g_delay_len - ) - port map ( - rst => i_rst, - clk => clk, - din => c_out_rst_level_n, - dout => o_rst - ); + without_pipe : if g_tree_len = 0 generate + u_async : entity work.common_async + generic map ( + g_rst_level => c_out_rst_level, + g_delay_len => g_delay_len + ) + port map ( + rst => i_rst, + clk => clk, + din => c_out_rst_level_n, + dout => out_rst + ); + end generate; -- 2024 -- Pass on synchronized reset with sufficient g_tree_len to ease timing -- closure by FF duplication in out_rst tree. Keep rst = '0' to break -- combinatorial path with in_rst to ease timing closure in the reset tree - -- network. Use g_tree_len = 0 for wire out_rst <= o_rst, so no reset tree - -- as in 2009. - u_pipe : entity work.common_pipeline_sl - generic map ( - g_pipeline => g_tree_len, - g_reset_value => c_out_rst_value - ) - port map ( - rst => '0', - clk => clk, - in_dat => o_rst, - out_dat => out_rst - ); + -- network. Use g_tree_len = 0 for no clocked reset tree as in 2009. + -- Instantiate u_async again to keep 2009 and 2024 completely independent. + -- To avoid delta-cycle differences due to e.g. out_rst <= o_rst when + -- g_tree_len = 0, that could lead to different results in a simulation tb. + with_pipe : if g_tree_len > 0 generate + u_async : entity work.common_async + generic map ( + g_rst_level => c_out_rst_level, + g_delay_len => g_delay_len + ) + port map ( + rst => i_rst, + clk => clk, + din => c_out_rst_level_n, + dout => o_rst + ); + + u_pipe : entity work.common_async + generic map ( + g_rst_level => c_out_rst_level, + g_delay_len => g_tree_len -- must be positive in common_async + ) + port map ( + rst => '0', + clk => clk, + din => o_rst, + dout => out_rst + ); + end generate; end str; diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd index 08ad5365defe15e0e22c3acc25a08d01082688be..e14f425292aaaee5e0bd97b513a2af8427357f75 100644 --- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd @@ -75,7 +75,8 @@ begin u_wr_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 3 + g_delay_len => 3, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, @@ -87,7 +88,8 @@ begin u_wr_init : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 4 + g_delay_len => 4, + g_tree_len => 0 ) port map ( in_rst => wr_rst, diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd index 32aaf05a36d63454b735525c1fa03e4e4248b8b4..f8e00f24c557d2b78b319d3e24a5308d838d851e 100644 --- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd @@ -94,7 +94,8 @@ begin u_wr_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 3 + g_delay_len => 3, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, @@ -106,7 +107,8 @@ begin u_wr_init : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 4 + g_delay_len => 4, + g_tree_len => 0 ) port map ( in_rst => wr_rst, diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd index 302f5c2225f88fc1a3bcc4abdbcfc0fd4951156d..117e229b281ec810f9e12ef8deb42b85dbfcd55a 100644 --- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd +++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd @@ -83,7 +83,8 @@ begin u_fifo_rst : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 4 + g_delay_len => 4, + g_tree_len => 0 -- assume if necessary g_tree_len > 0 is covered via input rst ) port map ( in_rst => rst, @@ -101,7 +102,8 @@ begin u_fifo_init : entity work.common_areset generic map ( g_rst_level => '1', - g_delay_len => 4 + g_delay_len => 4, + g_tree_len => 0 ) port map ( in_rst => fifo_rst, diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd index 87dcb12eb142c5d53e00317da795fa008325dae2..ecf317c77fd17dd47c98d402b590d1b94697b41f 100644 --- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd +++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd @@ -368,8 +368,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 4 -- 2 sync intervals should be sufficient, choose 4 to be safe (erko) ) diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd index 500b07e8b6b3f4604f1c70b802801cb80d4d9a2c..ae5d36ad86eefcb87632d611b3b4f45687dcef8e 100644 --- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd +++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd @@ -96,8 +96,6 @@ begin u_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => c_ctrl_fifo_depth ) @@ -120,8 +118,6 @@ begin u_error_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_error_w, g_nof_words => c_ctrl_fifo_depth ) @@ -144,8 +140,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 4 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 2 ) diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd index 4b486c78604c56df55dafdb845af7b523e38ce8f..cc84dee71bea2d11a30c2d2ed42ce8f050739ebe 100644 --- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd +++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd @@ -158,7 +158,7 @@ begin proc_common_gen_data(c_rl, c_init, rst, s_clk, cnt_en, ready, in_dat, in_val); -- Verify data - verify_data_en <= verify_en or dp_locked; + verify_data_en <= verify_en and dp_locked; verify_phase_en <= verify_en; proc_common_verify_data(c_rl, dp_sclk, verify_data_en, ready, dp_val, dp_sample_dat, prev_dp_sample_dat); diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd index 7909a2d68922b9044c750a5b63eabd4ad238ce82..b4ec6773d01b13f8c41c131dbe2cdcaac25da021 100644 --- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd +++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd @@ -324,8 +324,6 @@ begin u_sync_bsn_fifo : entity common_lib.common_fifo_sc generic map ( g_use_lut => true, -- Make this FIFO in logic, since it's only 2 words deep. - g_reset => false, - g_init => false, g_dat_w => c_dp_stream_bsn_w, g_nof_words => 16 )