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Commit 8b6ab695 authored by Reinier van der Walle's avatar Reinier van der Walle
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generated mmap gold files for unb2c_test

parent e9c44d8c
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boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.gold 0 → 100644
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View file @ 8b6ab695
fpga_name = unb2c_test
number_of_columns = 13
# There can be multiple lines with a single key. The host should ignore unknown keys.
# The lines with columns follow after the number_of_columns keys. The host should ignore
# the extra columns in case the mmap contains more columns than the host expects.
#
# col 1: mm_port_name, if - then it is part of previous MM port.
# col 2: number of peripherals, if - then it is part of previous peripheral.
# col 3: number of mm_ports, if - then it is part of previous MM port.
# col 4: mm_port_type, if - then it is part of previous MM port.
# col 5: field_name
# col 6: field start address (in MM words)
# col 7: number of fields, if - then it is part of previous field_name.
# col 8: field access_mode, if - then it is part of previous field_name.
# col 9: field radix, if - then it is part of previous field_name.
# col 10: field mm_mask
# col 11: field user_mask, if - then it is same as mm_mask
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00080000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00100000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00100000 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00180000 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00200000 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00200000 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00200400 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x00280000 1 RO uint32 b[29:0] - - -
- - - - stable 0x00280000 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00280000 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x00280001 1 RW uint32 b[27:0] - - -
- - - - edge 0x00280001 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x00280002 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x00300000 1 WO uint32 b[23:0] - - -
- - - - rden 0x00300001 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x00300002 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x00300003 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x00300004 1 WO uint32 b[0:0] - - -
- - - - busy 0x00300005 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x00300006 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x00380000 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x00380400 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x00400000 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x00400001 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x00400400 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x00480000 1 WO uint32 b[31:0] - - -
- - - - param 0x00480001 1 WO uint32 b[2:0] - - -
- - - - read_param 0x00480002 1 WO uint32 b[0:0] - - -
- - - - write_param 0x00480003 1 WO uint32 b[0:0] - - -
- - - - data_out 0x00480004 1 RO uint32 b[23:0] - - -
- - - - data_in 0x00480005 1 WO uint32 b[23:0] - - -
- - - - busy 0x00480006 1 RO uint32 b[0:0] - - -
REG_HEATER 1 1 REG enable 0x00500000 25 RW uint32 b[31:0] - - -
REG_DIAG_BG_1GBE 1 1 REG enable 0x00580000 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00580000 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00580001 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00580002 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00580003 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00580004 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00580005 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00580006 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00580007 - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_1GBE 1 2 RAM data 0x00580400 32 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00600000 1 RW uint32 b[2:0] - - 4
- - - - init 0x00600001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00600002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00600003 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_1GBE 1 2 REG xon_stable 0x00680000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00680000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00680000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00680001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00680002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00680003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00680004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00680005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00680006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00680007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00680008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_1GBE 1 2 REG sync_cnt 0x00700000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00700001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_1GBE 1 2 RAM data 0x00700400 20 RW uint32 b[31:0] - - 32
REG_DIAG_TX_SEQ_1GBE 1 2 REG control 0x00780000 1 RW uint32 b[1:0] - - 8
- - - - result 0x00780001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00780002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00780003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00780004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00780005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00780006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00780007 1 RW uint32 b[31:0] - - -
REG_DIAG_BG_10GBE 1 1 REG enable 0x00800000 1 RW uint32 b[0:0] - - -
- - - - enable_sync 0x00800000 1 RW uint32 b[1:1] - - -
- - - - samples_per_packet 0x00800001 1 RW uint32 b[31:0] - - -
- - - - blocks_per_sync 0x00800002 1 RW uint32 b[31:0] - - -
- - - - gapsize 0x00800003 1 RW uint32 b[31:0] - - -
- - - - mem_low_adrs 0x00800004 1 RW uint32 b[31:0] - - -
- - - - mem_high_adrs 0x00800005 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00800006 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00800007 - - - b[31:0] b[63:32] - -
RAM_DIAG_BG_10GBE 1 72 RAM data 0x00840000 1024 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x00840001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00880000 1 RW uint32 b[2:0] - - 4
- - - - init 0x00880001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00880002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00880003 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_10GBE 1 72 REG xon_stable 0x00900000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x00900000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00900000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00900001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00900002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00900003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00900004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00900005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00900006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00900007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00900008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_10GBE 1 72 REG sync_cnt 0x00980000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00980001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_10GBE 1 72 RAM data 0x009c0000 900 RW uint32 b[31:0] b[31:0] - 2048
- - - - - 0x009c0001 - - - b[31:0] b[63:32] - -
REG_DIAG_TX_SEQ_10GBE 1 72 REG control 0x00a00000 1 RW uint32 b[1:0] - - 8
- - - - result 0x00a00001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00a00002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00a00003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00a00004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00a00005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00a00006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00a00007 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_QSFP_RING 1 48 REG rx_transfer_control 0x00a80000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00a80001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00a80002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00a80040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00a80080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x00a800c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a800c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x00a800c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a800c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00a80100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00a80140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00a80800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00a80801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00a80802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00a80803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00a80804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00a80805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00a80806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00a80807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00a80808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00a80809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x00a8080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x00a8080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00a80818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00a80c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00a80c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00a80c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00a80c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00a80c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00a80c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00a80c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00a80c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00a80c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00a80c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00a80c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00a80c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00a80c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00a80c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00a80c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00a80c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00a80c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00a80c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00a80c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00a80c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00a80c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00a80c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00a80c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00a80c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00a80c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00a80c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00a80c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00a80c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00a80c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00a80c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00a80c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a80c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00a81001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00a81040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00a81080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x00a810c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a810c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00a81100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00a81140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00a81141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00a81142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00a81180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00a81181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00a81182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00a81183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00a81184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00a81185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00a81186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00a81187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00a81190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00a81191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00a81192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00a81193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00a81194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00a81195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00a81196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00a81197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x00a811a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00a81200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00a81201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00a81202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00a81801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00a81c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00a81c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00a81c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00a81c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00a81c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00a81c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00a81c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00a81c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00a81c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00a81c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00a81c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00a81c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00a81c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00a81c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00a81c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00a81c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00a81c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00a81c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00a81c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00a81c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00a81c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00a81c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00a81c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00a81c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00a81c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00a81c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00a81c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00a81c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00a81c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00a81c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00a81c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00a81c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_QSFP_RING 1 48 REG tx_snk_out_xon 0x00b00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00b00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00b00000 1 RO uint32 b[3:2] - - -
REG_TR_10GBE_BACK0 1 24 REG rx_transfer_control 0x00b80000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00b80001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00b80002 1 RW uint32 b[0:0] - - -
- - - - rx_padcrc_control 0x00b80040 1 RW uint32 b[1:0] - - -
- - - - rx_crccheck_control 0x00b80080 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_error 0x00b800c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b800c1 - - - b[31:0] b[31:0] - -
- - - - rx_pktovrflow_etherstatsdropevents 0x00b800c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b800c3 - - - b[31:0] b[31:0] - -
- - - - rx_lane_decoder_preamble_control 0x00b80100 1 RW uint32 b[0:0] - - -
- - - - rx_preamble_inserter_control 0x00b80140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_control 0x00b80800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_maxlength 0x00b80801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr0 0x00b80802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_addr1 0x00b80803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_0 0x00b80804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00b80805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00b80806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00b80807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00b80808 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00b80809 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x00b8080a 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x00b8080b 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00b80818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_clr 0x00b80c00 1 RW uint32 b[0:0] - - -
- - - - rx_stats_framesok 0x00b80c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c03 - - - b[31:0] b[31:0] - -
- - - - rx_stats_frameserr 0x00b80c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c05 - - - b[31:0] b[31:0] - -
- - - - rx_stats_framescrcerr 0x00b80c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c07 - - - b[31:0] b[31:0] - -
- - - - rx_stats_octetsok 0x00b80c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c09 - - - b[31:0] b[31:0] - -
- - - - rx_stats_pausemacctrl_frames 0x00b80c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0b - - - b[31:0] b[31:0] - -
- - - - rx_stats_iferrors 0x00b80c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0d - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_framesok 0x00b80c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c0f - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicast_frameserr 0x00b80c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c11 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastframesok 0x00b80c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c13 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicast_frameserr 0x00b80c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c15 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastframesok 0x00b80c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c17 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcast_frameserr 0x00b80c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c19 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatsoctets 0x00b80c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatspkts 0x00b80c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_undersizepkts 0x00b80c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c1f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_oversizepkts 0x00b80c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c21 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts64octets 0x00b80c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c23 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00b80c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c25 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00b80c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c27 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00b80c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c29 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00b80c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2b - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00b80c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2d - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00b80c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c2f - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_fragments 0x00b80c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c31 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstats_jabbers 0x00b80c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c33 - - - b[31:0] b[31:0] - -
- - - - rx_stats_etherstatscrcerr 0x00b80c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c35 - - - b[31:0] b[31:0] - -
- - - - rx_stats_unicastmacctrlframes 0x00b80c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c37 - - - b[31:0] b[31:0] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00b80c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c39 - - - b[31:0] b[31:0] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00b80c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c3b - - - b[31:0] b[31:0] - -
- - - - rx_stats_pfcmacctrlframes 0x00b80c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b80c3d - - - b[31:0] b[31:0] - -
- - - - tx_transfer_status 0x00b81001 1 RO uint32 b[0:0] - - -
- - - - tx_padins_control 0x00b81040 1 RW uint32 b[0:0] - - -
- - - - tx_crcins_control 0x00b81080 1 RW uint32 b[1:0] - - -
- - - - tx_pktunderflow_error 0x00b810c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b810c1 - - - b[31:0] b[31:0] - -
- - - - tx_preamble_control 0x00b81100 1 RW uint32 b[0:0] - - -
- - - - tx_pauseframe_control 0x00b81140 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_quanta 0x00b81141 1 RW uint32 b[15:0] - - -
- - - - tx_pauseframe_enable 0x00b81142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00b81180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_1 0x00b81181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_2 0x00b81182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_3 0x00b81183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00b81184 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00b81185 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00b81186 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00b81187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00b81190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00b81191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00b81192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00b81193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00b81194 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00b81195 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00b81196 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00b81197 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x00b811a0 1 RW uint32 b[7:0] - - -
- - - - tx_addrins_control 0x00b81200 1 RW uint32 b[0:0] - - -
- - - - tx_addrins_macaddr0 0x00b81201 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00b81202 1 RW uint32 b[15:0] - - -
- - - - tx_frame_maxlength 0x00b81801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_clr 0x00b81c00 1 RW uint32 b[0:0] - - -
- - - - tx_stats_framesok 0x00b81c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c03 - - - b[31:0] b[31:0] - -
- - - - tx_stats_frameserr 0x00b81c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c05 - - - b[31:0] b[31:0] - -
- - - - tx_stats_framescrcerr 0x00b81c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c07 - - - b[31:0] b[31:0] - -
- - - - tx_stats_octetsok 0x00b81c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c09 - - - b[31:0] b[31:0] - -
- - - - tx_stats_pausemacctrl_frames 0x00b81c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0b - - - b[31:0] b[31:0] - -
- - - - tx_stats_iferrors 0x00b81c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0d - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_framesok 0x00b81c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c0f - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicast_frameserr 0x00b81c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c11 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastframesok 0x00b81c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c13 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicast_frameserr 0x00b81c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c15 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastframesok 0x00b81c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c17 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcast_frameserr 0x00b81c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c19 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatsoctets 0x00b81c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatspkts 0x00b81c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_undersizepkts 0x00b81c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c1f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_oversizepkts 0x00b81c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c21 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts64octets 0x00b81c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c23 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00b81c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c25 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00b81c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c27 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00b81c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c29 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00b81c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2b - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00b81c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2d - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00b81c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c2f - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_fragments 0x00b81c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c31 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstats_jabbers 0x00b81c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c33 - - - b[31:0] b[31:0] - -
- - - - tx_stats_etherstatscrcerr 0x00b81c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c35 - - - b[31:0] b[31:0] - -
- - - - tx_stats_unicastmacctrlframes 0x00b81c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c37 - - - b[31:0] b[31:0] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00b81c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c39 - - - b[31:0] b[31:0] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00b81c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00b81c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00b81c3d - - - b[31:0] b[31:0] - -
REG_ETH10G_BACK0 1 24 REG tx_snk_out_xon 0x00c00000 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00c00000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00c00000 1 RO uint32 b[3:2] - - -
REG_IO_DDR_MB_I 1 1 REG burstbegin 0x00c80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00c80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00c80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00c80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00c80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00c80007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_I 1 1 REG control 0x00d00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00d00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00d00002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00d00003 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_I 1 1 REG control 0x00d80000 1 RW uint32 b[1:0] - - -
- - - - result 0x00d80001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00d80002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00d80003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00d80004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00d80005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00d80006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00d80007 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_I 1 1 REG sync_cnt 0x00e00000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x00e00001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_I 1 1 RAM data 0x00e00400 1024 RW uint32 b[31:0] - - -
REG_IO_DDR_MB_II 1 1 REG burstbegin 0x00e80000 1 WO uint32 b[0:0] - - -
- - - - wr_not_rd 0x00e80001 1 WO uint32 b[0:0] - - -
- - - - done 0x00e80002 1 RO uint32 b[0:0] - - -
- - - - address 0x00e80005 1 WO uint32 b[31:0] - - -
- - - - burstsize 0x00e80006 1 WO uint32 b[31:0] - - -
- - - - flush 0x00e80007 1 RW uint32 b[0:0] - - -
REG_DIAG_TX_SEQ_DDR_MB_II 1 1 REG control 0x00f00000 1 RW uint32 b[2:0] - - -
- - - - init 0x00f00001 1 RW uint32 b[31:0] - - -
- - - - tx_cnt 0x00f00002 1 RO uint32 b[31:0] - - -
- - - - modulo 0x00f00003 1 RW uint32 b[31:0] - - -
REG_DIAG_RX_SEQ_DDR_MB_II 1 1 REG control 0x00f80000 1 RW uint32 b[1:0] - - -
- - - - result 0x00f80001 1 RO uint32 b[1:0] - - -
- - - - rx_cnt 0x00f80002 1 RO uint32 b[31:0] - - -
- - - - rx_sample 0x00f80003 1 RO uint32 b[31:0] - - -
- - - - step_0 0x00f80004 1 RW uint32 b[31:0] - - -
- - - - step_1 0x00f80005 1 RW uint32 b[31:0] - - -
- - - - step_2 0x00f80006 1 RW uint32 b[31:0] - - -
- - - - step_3 0x00f80007 1 RW uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_DDR_MB_II 1 1 REG sync_cnt 0x01000000 1 RO uint32 b[31:0] - - -
- - - - word_cnt 0x01000001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_DDR_MB_II 1 1 RAM data 0x01000400 1024 RW uint32 b[31:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x01080000 1 RW uint32 b[30:0] - - -
- - - - reset 0x01080000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x01100014 1 RW uint32 b[16:0] - - 256
- - - - rx_syncn_sysref_ctrl 0x01100015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x01100015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x01100015 1 RW uint32 b[10:3] - - -
- - - - rx_csr_lmfc_offset 0x01100015 1 RW uint32 b[19:12] - - -
- - - - rx_err0 0x01100018 1 RW uint32 b[8:0] - - -
- - - - rx_err1 0x01100019 1 RW uint32 b[9:0] - - -
- - - - csr_dev_syncn 0x01100020 1 RO uint32 b[0:0] - - -
- - - - csr_rbd_count 0x01100020 1 RO uint32 b[10:3] - - -
- - - - rx_status1 0x01100021 1 RW uint32 b[23:0] - - -
- - - - rx_status2 0x01100022 1 RW uint32 b[23:0] - - -
- - - - rx_status3 0x01100023 1 RW uint32 b[7:0] - - -
- - - - rx_ilas_csr_l 0x01100025 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_f 0x01100025 1 RW uint32 b[15:8] - - -
- - - - rx_ilas_csr_k 0x01100025 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_m 0x01100025 1 RW uint32 b[31:24] - - -
- - - - rx_ilas_csr_n 0x01100026 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_cs 0x01100026 1 RW uint32 b[7:6] - - -
- - - - rx_ilas_csr_np 0x01100026 1 RW uint32 b[12:8] - - -
- - - - rx_ilas_csr_subclassv 0x01100026 1 RW uint32 b[15:13] - - -
- - - - rx_ilas_csr_s 0x01100026 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_jesdv 0x01100026 1 RW uint32 b[23:21] - - -
- - - - rx_ilas_csr_cf 0x01100026 1 RW uint32 b[28:24] - - -
- - - - rx_ilas_csr_hd 0x01100026 1 RW uint32 b[31:31] - - -
- - - - rx_status4 0x0110003c 1 RW uint32 b[15:0] - - -
- - - - rx_status5 0x0110003d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0110003e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0110003f 1 RO uint32 b[31:0] - - -
REG_BSN_SOURCE 1 1 REG dp_on 0x01180000 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x01180000 1 RW uint32 b[1:1] - - -
- - - - nof_block_per_sync 0x01180001 1 RW uint32 b[31:0] - - -
- - - - bsn 0x01180002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x01180003 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 12 REG xon_stable 0x01200000 1 RO uint32 b[0:0] - - 16
- - - - ready_stable 0x01200000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x01200000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x01200001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x01200002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x01200003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x01200004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x01200005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x01200006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x01200007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x01200008 1 RO uint32 b[31:0] - - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x01280000 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x01280001 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x01400000 131072 RW uint32 b[31:0] b[15:0] - 131072
\ No newline at end of file
boards/uniboard2c/designs/unb2c_test/unb2c_test.mmap.qsys.gold 0 → 100644
+ 593
− 0
View file @ 8b6ab695
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